A 33–41-GHz SiGe-BiCMOS Digital Step Attenuator With Minimized Unit Impedance Variation

Abstract

A 5-bit active digital step attenuator (DSA), which simultaneously achieves low amplitude and phase variations, is proposed for wideband phased-array applications. The input and output impedances for each attenuation unit under the reference state and the attenuation state can remain basically the same. Therefore, the amplitude and phase errors caused by a load impedance mismatch between each unit can be alleviated. Implemented in 130-nm silicon–germanium (SiGe) BiCMOS technology platform, the proposed DSA provides a maximum attenuation range of 15.5 dB with 0.5-dB steps. It exhibits an insertion loss (IL) less than 13 dB and input/output return losses less than −10 dB from 31 to 41 GHz. In addition, with the help of minimized amplitude and phase variations, the DSA exhibits a root-mean-square (rms) amplitude error less than 0.2 dB and an rms phase error less than 2.5° at 33–41 GHz, which are the lowest such errors ever reported. The chip core area of the DSA is 0.22 mm2 (0.5 mm $\times0.44$ mm). It shows a suitable performance for 5G applications.