A 37–40-GHz Low-Phase-Imbalance CMOS Attenuator With Tail-Capacitor Compensation Technique

Abstract

A Ka-band 5-bit CMOS digital step attenuator (DSA) with low phase variations for 5G applications is presented. The attenuator cell is optimized to alleviate the phase variations of conventional switched attenuators. A tail capacitor that is connected in series with the shunt resistor is used to construct a correction network with hyperbolic function characteristics. The DSA was implemented using a 65 nm CMOS process. It has a maximum attenuation range of 31 dB with 1.0 dB steps. With the help of the tail capacitor, the DSA exhibits a root-mean-square (rms) amplitude error less than 0.27 dB and a rms phase error less than 3.7° from 37-40 GHz, the lowest such errors ever reported. The active core layout area is 0.22 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> (0.51 mm × 0.42 mm). It shows suitable performance for 5G applications. The DSA is integrated into a phase-/amplitude-controlling chip to constitute a 5G system.