Abstract
This work presents a 24 GHz integrated Phase-Locked Loop in a 60 GHz sliding-IF transceiver for IEEE 802.15.3c standard with low phase noise. For low phase noise, a varactor and MOM cap combination method is applied in this 24 GHz PLL. The capacitor bank is optimized to decrease the noise folding from circuit noise to phase noise within this method. This analog PLL is fabricated in a 65 nm CMOS technology with a phase noise of −98.8 dBc/Hz@1 MHz, and the reference spur is −62.4 dBc. The power consumption of the PLL is 45.6 mW, including the output buffer.
Highlights
Typical applications in the 60 GHz ISM band, such as wireless highdefinition video streaming, require a quality reference signal to avoid the receiver sensitivity degradation [1] and improve transmitter signal quality
A varactor and MOM cap combination method is applied in this 24 GHz phase-locked loop (PLL)
This analog PLL is fabricated in a 65 nm CMOS technology with a phase noise of À98.8 dBc/ Hz@1 MHz, and the reference spur is À62.4 dBc
Summary
Typical applications in the 60 GHz ISM band, such as wireless highdefinition video streaming, require a quality reference signal to avoid the receiver sensitivity degradation [1] and improve transmitter signal quality. The frequency synthesizer's power consumption and phase noise are critical for an IEEE 802.15.3.c 60 GHz transceiver due to its direct relationship to communication data-rate and battery consumption rate. Conventional compound semiconductors such as gallium arsenide (GaAs) and indium phosphide (InP) are costly, bulky, low yield, and high-power consumption, which are not suitable for the consumer electronic market [2,3]. An image-reject filter is a method to overcome this problem It suffers from a trade-off between image rejection and channel selection.
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