A 570fs<inf>rms</inf> integrated-jitter ring-VCO-based 1.21GHz PLL with hybrid loop

Abstract

Sampling clock jitter significantly degrades the circuit performance and dynamic range of an ADC [1]. This paper presents a 570fs rms integrated-jitter 1.21GHz PLL with a hybrid loop. A ring VCO has a much inferior phase noise characteristic as compared to an LC VCO, but its area efficiency is attractive. To suppress the phase noise of a ring VCO, a wide-loop-bandwidth PLL with sufficiently low in-band noise is indispensable. An all-digital PLL (ADPLL) [2] has insufficiently low in-band phase noise because of the quantization error of the time-to-digital converter (TDC) without employing additional techniques such as power-hungry time amplification [3]. On the other hand, a conventional analog PLL has a superior in-band phase noise but needs a large loop-filter capacitor to maintain a wide tuning range due to a high control sensitivity of the ring VCO. The dual-tuning topology is useful for minimizing the size of the loop filter while maintaining low in-band phase noise [4, 5]. However, it also suffers from strong reference spurs, as it is the case in the conventional analog PLL having a wide loop bandwidth. The proposed PLL employs a hybrid loop consisting of a type-II ADPLL and a type-I analog PLL. The type-II ADPLL enables the wide tuning range without a large loop-filter capacitor. The loop-filter capacitor in the analog PLL is also minimized since it does not need to cover a wide tuning range. The analog PLL eliminates the residual quantization error of the TDC in the ADPLL and achieves a sufficiently low in-band phase noise. Overall, the proposed PLL suppresses the phase noise contribution from the ring digital/voltage-controlled oscillator (DVCO).