Abstract

A novel, low power frequency synthesiser system with 60 MHz output bandwidth is reported which is suitable for integration in a single chip RF transceiver. The system is based upon a conventional DDFS architecture. However, the problems which usually arise from the non-ideal behaviour of the DAC and the high power consumption of a ROM are avoided by using a non-volatile analogue memory array. Simulation results are presented which show that the system is suitable for use in an RF transceiver.

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.