Abstract
A novel, low power frequency synthesiser system with 60 MHz output bandwidth is reported which is suitable for integration in a single chip RF transceiver. The system is based upon a conventional DDFS architecture. However, the problems which usually arise from the non-ideal behaviour in the DAC and the high power consumption of a ROM are avoided by using a non-volatile analogue memory array. Simulation results are presented which show that the system is suitable for use in an RF transceiver. (6 pages)
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