A 12-Bit 1 GS/s RF Sampling Pipeline-SAR ADC With Harmonic Injecting Cross-Coupled Pair Achieving 7.5 fj/Conv-Step

Abstract

We present an RF sampling 1 GS/s 12-bit single-channel successive approximation register (SAR) assisted pipeline analog to digital converter (ADC). A novel Harmonic-injecting Cross-Coupled Pair (HXCP) is proposed in a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{G}_{\text {m}}$ </tex-math></inline-formula> -R based residue amplifier design as a critical part of the presented ADC. This technique overcomes the challenges in designing analog amplifiers using advanced nanometer CMOS processes and achieves the gain and linearity required for the ADC. By implementing the HXCP in a residue amplifier (RA), the proposed technique successfully improves the RA linearity by at least 10 dB and meanwhile boosts the gain of the RA to be about 8. The entire ADC consists of three stages each with 4-bit, 4-bit, and 6-bit, respectively. Two one-bit interstage redundancies are implemented between the three stages. Various techniques are also implemented to help the ADC achieve the targeted speed and resolution. The presented ADC was implemented in a 28nm CMOS process and achieves an ERBW of 1 GHz, an SNDR of 60.7 dB, an SFDR of 73 dB at Nyquist input (495 MHz) and an SFDR of 82 dB at 1 GHz input. A 7.5 fj/conv-step FoM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">w</sub> and a 169.4 dB FoMs are achieved, which demonstrate one of the best Figure of Merits (FoMs) among ADCs of similar speed and resolution.