5 - Images and High-Speed Processing

Abstract

This chapter explores how a high-level specification can be practically decomposed into a series of manageable problems that may all have a relatively simple solution. The key to successful systems design is to decompose the design into blocks that have a definable core function. This can then be implemented directly in VHSIC hardware description language (VHDL), where VHSIC stands for very high speed integrated circuit. The other important aspect of the design is to analyze the boundaries. A VHDL design can be easily constructed if a designer knows the core functionality. However, getting the individual blocks to communicate successfully is often much harder. As a result, the designer often spends a lot of debug time in integrating a number of different functions together and being forced to rewrite large sections of code to make that happen. A useful approach to handling this specific problem is to create “empty” VHDL models that do not operate functionally. These models can be tested with basic communications test data. The chapter provides a useful introduction to modeling and designing complex systems using VHDL.