Abstract
This chapter explores the Finite State Machines (FSMs) in VHSIC hardware description language (VHDL), where VHSIC stands for very high speed integrated circuit. The basic idea of a FSM is to store a sequence of different unique states and transition between them depending on the values of the inputs and the current state of the machine. The FSM can be of two types: Moore, where the output of the state machine is purely dependent on the state variables and Mealy, where the output can depend on the current state variable values and the input values. The general structure of an FSM is shown in this chapter using an illustrative figure. The chapter describes the state transition diagrams and then discusses the implementation of FSM in VHDL. The state transition diagrams are used to describe FSM from a design point of view. FSM are a fundamental technique for designing control algorithms in digital hardware.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
