200-V High-side thick-layer SOI field p-channel LDMOS with multiple field plates

Abstract

A high-voltage thick layer SOI field p-channel LDMOS (pLDMOS) with multiple field plates based on 11-μm-thick silicon layer and 1-μm-thick buried oxide layer is presented in this paper. The thick gate oxide layer is formed by field oxide process to endure the high voltage between the source and gate electrodes. The field implant (FI) technology is adopted to eliminate channel discontinuity at the bird's beak region. Multiple field plates constructed by polysilicon and metal layer are adopted to modulate electric field distribution of the depleted drift region. The SOI field pLDMOS with off-state breakdown voltage (BV) of −240 V is experimentally realized, which can be widely used for simplifying the design of level shifting.