2.1 dB noise figure 5.2 GHz CMOS low noise amplifier using wafer-level integrated passive device technology with a DC power consumption of 10 mW

Abstract

This work presents an inductor with a high quality factor (Q) that is fabricated using wafer-level integrated passive device (IPD) technology and a 5.2 GHz differential low noise amplifier (DLNA) in a Taiwan semiconductor manufacturing company (TSMC™) 0.18 µm complementary metal-oxide-semiconductor (CMOS) process. The IPD inductors were stacked on top of a CMOS DLNA. The use of IPD inductors in the input matching network (IMN) is an efficient alternative to on-chip inductors for mass production. The performance of the DLNA with and without an IPD inductor is studied. The IPD CMOS-DLNA achieves a noise figure (NF) of 2.1 dB with a power consumption of 10 mW. The measured NF of the CMOS-IPD DLNA is 0.6 dB better than that of the typical CMOS DLNA at the same power consumption. The CMOS-IPD DLNA achieves the best figure of merit of any of the recently described 5–6 GHz CMOS LNAs.