ZnO Nanowire Transistors Research Articles

ZnO nanowire optoelectronic synapse for neuromorphic computing

Artificial synapses that integrate functions of sensing, memory and computing are highly desired for developing brain-inspired neuromorphic hardware. In this work, an optoelectronic synapse based on the ZnO nanowire (NW) transistor is achieved, which can be used to emulate both the short-term and long-term synaptic plasticity. Synaptic potentiation is present when the device is stimulated by light pulses, arising from the light-induced O2 desorption and the persistent photoconductivity behavior of the ZnO NW. On the other hand, synaptic depression occurs when the device is stimulated by electrical pulses in dark, which is realized by introducing a charge trapping layer in the gate dielectric to trap carriers. Simulation of a neural network utilizing the ZnO NW synapses is carried out, demonstrating a high recognition accuracy over 90% after only 20 training epochs for recognizing the Modified National Institute of Standards and Technology digits. The present nanoscale optoelectronic synapse has great potential in the development of neuromorphic visual systems.

Photo-assisted hysteresis of electronic transport for ZnO nanowire transistors

Recently, ZnO nanowire field effect transistors (FETs) have received renewed interest due to their extraordinary low dimensionality and high sensitivity to external chemical environments and illumination conditions. These prominent properties have promising potential in nanoscale chemical and photo-sensors. In this article, we have fabricated ZnO nanowire FETs and have found hysteresis behavior in their transfer characteristics. The mechanism and dynamics of the hysteresis phenomena have been investigated in detail by varying the sweeping rate and range of the gate bias with and without light irradiation. Significantly, light irradiation is of great importance on charge trapping by regulating adsorption and desorption of oxygen at the interface of ZnO/SiO2. Carriers excited by light irradiation can dramatically promote trapping/detrapping processes. With the assistance of light illumination, we have demonstrated a photon-assisted nonvolatile memory which employs the ZnO nanowire FET. The device exhibits reliable programming/erasing operations and a large on/off ratio. The proposed proto-type memory has thus provided a possible novel path for creating a memory functionality to other low-dimensional material systems.

Source‐gating effect in hydrothermally grown ZnO nanowire transistors

Nanowire source‐gated field‐effect transistors (NW SGT) are demonstrated using hydrothermally grown ZnO NWs. Device quality ZnO NWs with moderate n‐type doping are achieved by thermal annealing in ambient air at ∼550 °C. A single ZnO NW device with Au source‐drain contacts (s/d) is found to operate under source‐gating mode, with characteristics markedly different from a reference device with ohmic contacts. The NW SGT shows exceptionally early drain current–voltage saturation (IDSAT–VDSAT) below 1 V. The change in saturation with the gate voltage (VG) is over 80 times lower than a reference device with ohmic contacts. This device behavior is attributed to the source‐gate overlap, enabling gate field penetration inside the depleted source. Current modulation is obtained by a combination of gate‐induced image force barrier lowering and the high internal electric fields at source pinch‐off. Effective Schottky barrier heights are extracted from activation energy measurements, revealing systematic barrier lowering with increasing VG. These features of the device lead us to conclude that the single NW field‐effect transistor (FET) with Schottky contacts operated under SGT mode.

High-gain subnanowatt power consumption hybrid complementary logic inverter with WSe2 nanosheet and ZnO nanowire transistors on glass.

A 1D-2D hybrid complementary logic inverter comprising of ZnO nanowire and WSe2 nanosheet field-effect transistors (FETs) is fabricated on glass, which shows excellent static and dynamic electrical performances with a voltage gain of ≈60, sub-nanowatt power consumption, and at least 1 kHz inverting speed.

Effect of atomic layer deposition temperature on the performance of top-down ZnO nanowire transistors.

This paper studies the effect of atomic layer deposition (ALD) temperature on the performance of top-down ZnO nanowire transistors. Electrical characteristics are presented for 10-μm ZnO nanowire field-effect transistors (FETs) and for deposition temperatures in the range 120°C to 210°C. Well-behaved transistor output characteristics are obtained for all deposition temperatures. It is shown that the maximum field-effect mobility occurs for an ALD temperature of 190°C. This maximum field-effect mobility corresponds with a maximum Hall effect bulk mobility and with a ZnO film that is stoichiometric. The optimized transistors have a field-effect mobility of 10 cm2/V.s, which is approximately ten times higher than can typically be achieved in thin-film amorphous silicon transistors. Furthermore, simulations indicate that the drain current and field-effect mobility extraction are limited by the contact resistance. When the effects of contact resistance are de-embedded, a field-effect mobility of 129 cm2/V.s is obtained. This excellent result demonstrates the promise of top-down ZnO nanowire technology for a wide variety of applications such as high-performance thin-film electronics, flexible electronics, and biosensing.

High-performance ZnO nanowire transistors with aluminum top-gate electrodes and naturally formed hybrid self-assembled monolayer/AlO(x) gate dielectric.

A method for the formation of a low-temperature hybrid gate dielectric for high-performance, top-gate ZnO nanowire transistors is reported. The hybrid gate dielectric consists of a self-assembled monolayer (SAM) and an aluminum oxide layer. The thin aluminum oxide layer forms naturally and spontaneously when the aluminum gate electrode is deposited by thermal evaporation onto the SAM-covered ZnO nanowire, and its formation is facilitated by the poor surface wetting of the aluminum on the hydrophobic SAM. The hybrid gate dielectric shows excellent electrical insulation and can sustain voltages up to 6 V. ZnO nanowire transistors utilizing the hybrid gate dielectric feature a large transconductance of 50 μS and large on-state currents of up to 200 μA at gate-source voltages of 3 V. The large on-state current is sufficient to drive organic light-emitting diodes with an active area of 6.7 mm(2) to a brightness of 445 cd/m(2). Inverters based on ZnO nanowire transistors and thin-film carbon load resistors operate with frequencies up to 30 MHz.

High performance non-volatile ferroelectric copolymer memory based on a ZnO nanowire transistor fabricated on a transparent substrate

A high performance ferroelectric non-volatile memory device based on a top-gate ZnO nanowire (NW) transistor fabricated on a glass substrate is demonstrated. The ZnO NW channel was spin-coated with a poly (vinylidenefluoride-co-trifluoroethylene) (P(VDF-TrFE)) layer acting as a top-gate dielectric without buffer layer. Electrical conductance modulation and memory hysteresis are achieved by a gate electric field induced reversible electrical polarization switching of the P(VDF-TrFE) thin film. Furthermore, the fabricated device exhibits a memory window of ∼16.5 V, a high drain current on/off ratio of ∼105, a gate leakage current below ∼300 pA, and excellent retention characteristics for over 104 s.

Programmable ZnO nanowire transistors using switchable polarization of ferroelectric liquid crystal

We demonstrate modulations of electrical conductance and hysteresis behavior in ZnO nanowire transistors via electrically polarized switching of ferroelectric liquid crystal (FLC). After coating a nanowire channel in the transistors with FLCs, we observed large increases in channel conductance and hysteresis width, and a strong dependence of hysteresis loops on the polarization states associated with the orientation of electric dipole moments along the direction of the gate electric field. Furthermore, the reversible switching and retention characteristics provide the feasibility of creating a hybrid system with switch and memory functions.

Photostable Zn2SnO4 Nanowire Transistors for Transparent Displays

Although oxide nanowires offer advantages for next-generation transparent display applications, they are also one of the most challenging materials for this purpose. Exposure of semiconducting channel areas of oxide nanowire transistors produces an undesirable increase in the photocurrent, which may result in unstable device operation. In this study, we have developed a Zn(2)SnO(4) nanowire transistor that operates stably regardless of changes in the external illumination. In particular, after exposure to a light source of 2100 lx, the threshold voltage (V(th)) showed a negative shift of less than 0.4 V, and the subthreshold slope (SS) changed by ∼0.1 V/dec. ZnO or SnO(2) nanowire transistors, in contrast, showed 1.5-2.0 V negative shift in V(th) and an SS change of ∼0.3 V/dec under the same conditions. Furthermore, the Zn(2)SnO(4) nanowire transistors returned to their initial state immediately after the light source was turned off, unlike those using the other two nanowires. Thus, Zn(2)SnO(4) nanowires achieve photostability without the application of a black material or additional processing, minimizing the photocurrent effect for display devices.

Horizontally aligned ZnO nanowire transistors using patterned graphene thin films

Here we report the directed growth of ZnO nanowires on multilayer graphene films (MGFs) without the use of metal seed materials. The ZnO source substance was diffused onto the MGF surface, where nanowires tended to grow in the high surface energy sites. This property was exploited to fabricate top-gate structural nanowire transistors with ZnO nanowires grown in the direction of the exposed sides of 6 × 4 μm patterned MGFs with a SiO2 capping layer. The devices showed an on-current of 160 nA, a threshold voltage of −2.27 V, an on-off current ratio of 3.98 × 105, and a field effect mobility of ∼41.32 cm2/V·s.

Direct growth of oxide nanowires on CuOx thin film

Oxide nanowires were directly grown on a CuOx thin film deposited by plasma-enhanced atomic layer deposition without additional metal catalysts. Oxide nanowires would exhibit metal–catalyst-free growth on the CuOx thin film with oxide materials diffused on the top. Through a focused ion beam and transmission electron microscopy, we could verify that SnO2 and ZnO nanowires were grown as single-crystalline structures just above the CuOx thin film. Bottom-gate structural SnO2 and ZnO nanowire transistors exhibited mobilities of 135.2 and 237.6 cm2 V−1 s−1, respectively. We anticipate that a variety of large-area and high-density oxide nanowires can be grown at low cost by using the CuOx thin film.

Top-Gate ZnO Nanowire Transistors and Integrated Circuits with Ultrathin Self-Assembled Monolayer Gate Dielectric

A novel approach for the fabrication of transistors and circuits based on individual single-crystalline ZnO nanowires synthesized by a low-temperature hydrothermal method is reported. The gate dielectric of these transistors is a self-assembled monolayer that has a thickness of 2 nm and efficiently isolates the ZnO nanowire from the top-gate electrodes. Inverters fabricated on a single ZnO nanowire operate with frequencies up to 1 MHz. Compared with metal-semiconductor field-effect transistors, in which the isolation of the gate electrode from the carrier channel relies solely on the depletion layer in the semiconductor, the self-assembled monolayer dielectric leads to a reduction of the gate current by more than 3 orders of magnitude.

ZnO nanowire transistor inverter using top-gate electrodes with different work functions

ZnO-nanowire field effect transistors (FETs) with a top gate Al2O3 dielectric and different metal electrodes were fabricated to form a low voltage electrical inverter. Two FETs with Pd and Ni/Ti gates whose respective work functions are so different as 5.3 and 4.3 eV were chosen to play as driver and load, since such different work functions lead to a threshold voltage (VT) difference of at least 1 V between the two FETs. Our FETs with Pd and Ni/Ti, respectively, showed 0.8 and −0.3 V for their VT values, while our inverter exhibited a desirable voltage transfer characteristics with voltage gain of over 15 during low voltage electrical gating.

Effect of grain boundary on electric performance of ZnO nanowire transistor with wrap-around gate

A novel grain boundary (GB) model characterized with different angles and positions in the nanowire was set up. By means of device simulator, the effects of grain boundary angle and location on the electrical performance of ZnO nanowire FET (Nanowire Field-Effect Transistor) with a wrap-around gate configuration, were explored. With the increase of the grain boundary angle, the electrical performance degrades gradually. When a grain boundary with a smaller angle, such as 5° GB, is located close to the source or drain electrode, the grain boundary is partially depleted by an electric field peak, which leads to the decrease of electron concentration and the degradation of transistor characteristics. When the 90° GB is located at the center of the nanowire, the action of the electric field is balanced out, so the electrical performance of transistor is better than that of the 90° GB located at the other positions.

Enhancement in the photodetection of ZnO nanowires by introducing surface-roughness-inducedtraps

We investigated the enhanced photoresponse of ZnO nanowire transistors that wasintroduced with surface-roughness-induced traps by a simple chemical treatment withisopropyl alcohol (IPA). The enhanced photoresponse of IPA-treated ZnO nanowiredevices is attributed to an increase in adsorbed oxygen on IPA-induced surfacetraps. The results of this study revealed that IPA-treated ZnO nanowire devicesdisplayed higher photocurrent gains and faster photoswitching speed than transistorscontaining unmodified ZnO nanowires. Thus, chemical treatment with IPA canbe a useful method for improving the photoresponse of ZnO nanowire devices.

Nonvolatile Memory Functionality of ZnO Nanowire Transistors Controlled by Mobile Protons

We demonstrated the nonvolatile memory functionality of ZnO nanowire field effect transistors (FETs) using mobile protons that are generated by high-pressure hydrogen annealing (HPHA) at relatively low temperature (400 °C). These ZnO nanowire devices exhibited reproducible hysteresis, reversible switching, and nonvolatile memory behaviors in comparison with those of the conventional FET devices. We show that the memory characteristics are attributed to the movement of protons between the Si/SiO(2) interface and the SiO(2)/ZnO nanowire interface by the applied gate electric field. The memory mechanism is explained in terms of the tuning of interface properties, such as effective electric field, surface charge density, and surface barrier potential due to the movement of protons in the SiO(2) layer, consistent with the UV photoresponse characteristics of nanowire memory devices. Our study will further provide a useful route of creating memory functionality and incorporating proton-based storage elements onto a modified CMOS platform for FET memory devices using nanomaterials.

Coulomb oscillations of indium-doped ZnO nanowire transistors in a magnetic field

We report on the observation of Coulomb oscillations from localized quantum dots superimposed on the normal hopping current in ZnO nanowire transistors. The Coulomb oscillations can be resolved up to 20 K. Positive anisotropic magnetoresistance has been observed due to the Lorentz force on the carrier motion. Magnetic field-induced tunneling barrier transparency results in an increase in oscillation amplitude with increasing magnetic field. The energy shift as a function of magnetic field indicates electron wave function modification in the quantum dots.

Novel Nonvolatile Memory with Multibit Storage Based on a ZnO Nanowire Transistor

We demonstrate a room temperature processed ferroelectric (FE) nonvolatile memory based on a ZnO nanowire (NW) FET where the NW channel is coated with FE nanoparticles. A single device exhibits excellent memory characteristics with the large modulation in channel conductance between ON and OFF states exceeding 10(4), a long retention time of over 4 × 10(4) s, and multibit memory storage ability. Our findings provide a viable way to create new functional high-density nonvolatile memory devices compatible with simple processing techniques at low temperature for flexible devices made on plastic substrates.

Site‐Specific Self‐Assembled Liquid‐Gated ZnO Nanowire Transistors for Sensing Applications

A scalable bottom-up solution-based approach for the site-specific realization of ZnO nanowire (ZnO-NW)-based field-effect transistors for sensing applications in liquids is reported. The nanowires are grown across predefined electrodes patterned by photolithography. Site specificity is attained by the use of nanoparticles acting as seeds. Using integrated on-chip microchannels and microfabricated gate electrodes, electrochemically gated ZnO-NW network transistors functioning in liquids are demonstrated. The optimized devices are rendered sensitive to pH through chemical functionalization. The unique combination of the sensitivity, site specificity, scalability, and cost effectiveness of the technique opens up avenues for the routine realization of one-dimensional nanostructure-based chemical and biosensors for analytical and diagnostic applications.

Large-Area Fabrication of Patterned ZnO-Nanowire Arrays Using Light Stamping Lithography

We demonstrate selective adsorption and alignment of ZnO nanowires on patterned poly(dimethylsiloxane) (PDMS) thin layers with (aminopropyl)siloxane self-assembled monolayers (SAMs). Light stamping lithography (LSL) was used to prepare patterned PDMS thin layers as neutral passivation regions on Si substrates. (3-Aminopropyl)triethoxysilane-based SAMs were selectively formed only on regions exposing the silanol groups of the Si substrates. The patterned positively charged amino groups define and direct the selective adsorption of ZnO nanowires with negative surface charges in the protic solvent. This procedure can be adopted in automated printing machines that generate patterned ZnO-nanowire arrays on large-area substrates. To demonstrate its usefulness, the LSL method was applied to prepare ZnO-nanowire transistor arrays on 4-in. Si wafers.