Zero Temperature Coefficient Research Articles

Microwave dielectric properties of (1 − x)ZnNb2O6–xBa(Zn1/3Nb2/3)O3 compound ceramic with near zero temperature coefficient

The phase composition, microstructures, sintering behavior, and microwave dielectric properties of (1 − x)ZnNb2O6–xBa(Zn1/3Nb2/3)O3 (x = 0.25, 0.30, 0.35, 0.40) ceramics prepared via conventional solid-state route were systematically investigated as a function of x value and sintering temperature. The ixiolite ZnNb2O6, perovskite Ba(Zn1/3Nb2/3)O3, and a minor phase of Ba3Zn1/3Nb14/3O15 were obtained throughout the studied compositional range. The variation of bulk density and dielectric properties are related to the x value. With increasing molar fraction of Ba(Zn1/3Nb2/3)O3, the temperature coefficient of resonant frequency (τ f ) value decreased, and a near-zero τ f value could be obtained for the samples with x = 0.30. The optimum microwave dielectric properties with an e r value of 31.22, a Q × f value of 39,611 GHz (at 5.5 GHz), and a τ f value of − 2.28 ppm/°C were obtained for 0.7ZnNb2O6–0.3Ba(Zn1/3Nb2/3)O3 ceramics sintered at 1200 °C for 4 h, which showed dense microstructures as well as well-developed grain growth.

Evaluation of SiC Schottky Diodes Using Pressure Contacts

The thermomechanical reliability of SiC power devices and modules is increasingly becoming of interest especially for high-power applications, where power cycling performance is critical. Press-pack assemblies are a trusted and reliable packaging solution that has traditionally been used for high-power thyristor-based applications in FACTS/HVDC, although press-pack IGBTs have become commercially available more recently. These press-pack IGBTs require antiparallel PiN diodes for enabling reverse conduction capability. In these high-power applications, paralleling chips for high current conduction capability is a requirement, hence, electrothermal stability during current sharing is critical. SiC Schottky diodes not only exhibit the advantages of wide bandgap technology compared to silicon PiN diodes, but they have significantly lower zero temperature coefficient (ZTC), meaning they are more electrothermally stable. The lower ZTC is due to the unipolar nature of SiC Schottky diodes as opposed to the bipolar nature of PiN diodes. This paper investigates the implementation and reliability of SiC Schottky diodes in press-pack assemblies. The impact of pressure loss on the electrothermal stability of parallel devices is investigated.

Zero temperature coefficient of resistance of the electrical-breakdown path in ultrathin hafnia

The recent widespread attention on the use of the non-volatile resistance switching property of a microscopic oxide region after electrical breakdown for memory applications has prompted basic interest in the conduction properties of the breakdown region. Here, we report an interesting crossover from a negative to a positive temperature dependence of the resistance of a breakdown region in ultrathin hafnia as the applied voltage is increased. As a consequence, a near-zero temperature coefficient of resistance is obtained at the crossover voltage. The behavior may be modeled by (1) a tunneling-limited transport involving two farthest-spaced defects along the conduction path at low voltage and (2) a subsequent transition to a scattering-limited transport after the barrier is overcome by a larger applied voltage.

Evaluation of heavy-ion impact in bulk and FDSOI devices under ZTC condition

This work examines the effects of heavy-ion impact under temperature variation. A NMOS device in 32nm bulk and 28nm FDSOI were analysed through TCAD simulations. In order to overcome the temperature effects, both devices were conducted to the Zero Temperature Coefficient (ZTC) condition. The results demonstrate a reduction from 5% up to 18% on the total collected charge and lower variation due to temperature fluctuation when the devices are operating in ZTC condition.

Effects of lithium fluoride addition on sintering characteristics and microwave dielectric properties of rock–salt structure Li2Mg4TiO7 ceramics

Li2Mg4TiO7 ceramics doped with 1–5 wt% LiF were successfully prepared by the conventional solid-state method. The sintered samples could be well indexed as the rock salt structure with space group Fm-3m (JCPDS #70-2711). The sintering behaviors, phase compositions, microstructures and microwave dielectric properties of ceramics were associated with the sintering temperature and the amount of LiF addition. The e r and Q·f values of the Li2Mg4TiO7 ceramics increased firstly and then decreased with increasing the amount of LiF addition. A near zero temperature coefficient of resonant of frequency (τ f ) value could be obtained by adjusting the amount of LiF additions. The Li2Mg4TiO7 ceramics doped with 2 wt% LiF sintered at 950 °C for 4 h possessed promising microwave dielectric properties with e r value of 14.43, Q·f value of 48,700 GHz and τ f value of −3.83 ppm/°C, making them suitable for low-temperature co-fired ceramic applications.

Improved dielectric resonator through Nd substitution in SrLa 4 Ti 4 O 15 ceramics at microwave frequencies

Abstract The effects of neodymium substitution on the sintering temperature and microwave dielectric properties of SrLa 4 Ti 4 O 15 were investigated. A single-phase solid solution with a hexagonal structure was formed in Sr(La 1−x Nd x ) 4 Ti 4 O 15 (x = 0.01–0.1) ceramics. By increasing x from 0.01 to 0.07, the dielectric constant and Q×f value of the sample increased at a sintering temperature of 1590 °C and thereafter decreased. In addition, the increase in the dielectric constant and Q×f value with increasing sintering temperature was in agreement with the increase in density in the composition range of 0.01–0.1. The zero temperature coefficient of resonant frequency of the Sr(La 1−x Nd x ) 4 Ti 4 O 15 (x = 0.01–0.1) ceramics also improved with increasing Nd content. Nd substitution resulted in excellent microwave dielectric properties, obtaining e r = 47.5, Q×f = 49,900 GHz, and τ f = 0.54 ppm/°C for the x = 0.07 composition.

Variation of Threshold Voltage With Temperature in Impact Ionization-Induced Steep Switching Si and Ge Junctionless MOSFETs

In this paper, we report on the anomalous behavior of threshold voltage ( ${V} _{\sf th})$ with temperature in junctionless (JL) transistors. It is shown that both positive and negative values of temperature coefficient of threshold voltage ( dV $_{\sf th}$ / dT ) in nMOS Si and Ge JL devices can occur at higher drain biases. At lower temperatures, ${V} _{\sf th}$ reduces with a decrease in temperature due to the dominance of bipolar effects over thermal generation of carriers, whereas at higher temperatures, thermal generation results in essentially unipolar characteristics, and ${V} _{\sf th}$ reduces with increase in temperature. It is also shown that zero temperature coefficient condition shall be nonexistent under dominant bipolar conduction over unipolar operation. Results show new viewpoints to understand the two contrasting physical mechanisms leading to positive and negative dV $_{\sf th}$ / dT values in JL devices.

Flexible Dielectric Nanocomposites with Ultrawide Zero-Temperature Coefficient Windows for Electrical Energy Storage and Conversion under Extreme Conditions.

Polymer dielectrics offer key advantages over their ceramic counterparts such as flexibility, scalability, low cost, and high breakdown voltages. However, a major drawback that limits more widespread application of polymer dielectrics is their temperature-dependent dielectric properties. Achieving dielectric constants with low/zero-temperature coefficient (L/0TC) over a broad temperature range is essential for applications in diverse technologies. Here, we report a hybrid filler strategy to produce polymer composites with an ultrawide L/0TC window of dielectric constant, as well as a significantly enhanced dielectric value, maximum energy storage density, thermal conductivity, and stability. By creating a series of percolative polymer composites, we demonstrated hybrid carbon filler based composites can exhibit a zero-temperature coefficient window of 200 °C (from -50 to 150 °C), the widest 0TC window for all polymer composite dielectrics reported to date. We further show the electric and dielectric temperature coefficient of the composites is highly stable against stretching and bending, even under AC electric field with frequency up to 1 MHz. We envision that our method will push the functional limits of polymer dielectrics for flexible electronics in extreme conditions such as in hybrid vehicles, aerospace, power electronics, and oil/gas exploration.

A sub-1V, 120 nW, PVT-variation Tolerant, Tunable and Scalable Voltage Reference with 60 d

This paper presents a novel low-power process, voltage and temperature (PVT)-variation tolerant voltage reference generator that can be easily redesigned across various CMOS technologies. The proposed circuit architecture can be used in standalone analog integrated circuits that may not require nano-scale technologies as well as system-on-a-chip applications that need analog circuits in a much lower technology node due to their dominant digital counterparts. The reference generator implements weighted averaging of a PTAT (proportional to absolute temperature) and a CTAT (complementary to absolute temperature) voltage at zero temperature coefficient (ZTC) point. PVT-variation tolerant behavior is achieved by using an on-chip shift register based switching circuit that adjusts the bias current of a key transistor in the circuit. The proposed reference generator is fabricated in 180 nm mixed-mode CMOS technology and also designed in 65 and 28 nm technologies using foundry provided models. For a temperature range from ${\mathbf 0}$ to 75 °C at 1.8 V supply, the measured tuned output voltage varies by only ${\pm 0.33}$ % across ${\mathbf 17}$ chips, which is significantly lower than all previously reported works.

Near zero temperature coefficient of resistance in Ti:Si:O thin films deposited by magnetron co-sputtering

Thin films of titanium/silicon/oxygen (Ti:Si:O) deposited by sputtering were evaluated as thin film resistors and the resulting resistance and temperature coefficient of resistance (TCR) was studied. The films were deposited in an Argon atmosphere at room temperature with 1% oxygen and their electrical properties evaluated before and after forming gas (5% H2: 95% N2) annealing at 325 and 450 °C for 1 h. The physical structure was characterized by x-ray diffraction (XRD), elemental composition and depth profile by Rutherford backscattering (RBS), and film composition by x-ray photoelectron spectroscopy (XPS). Carrier mobility, type and concentration were evaluated by Hall effect measurements. Thin films with a Ti:Si ratio of 1.6 exhibited a near zero TCR (−405 ppm °C−1) and sheet resistance (Rsh) at 25 °C of 1 kOhm sq−1.

Surface Acoustic Wave Devices Based on High Quality Temperature-Compensated Substrates

We report surface acoustic wave (SAW) devices based on two kinds of novel and optimized high quality piezoelectric substrates. SAW devices with excellent temperature stability and electromechanical coupling coefficient using the layered structures LiTaO3 (LT)/Si and LiNbO3 (LN)/SiO2/Si as the substrates are fabricated. These structures exhibit superior temperature performance than the conventional LT, LN substrates and reported related works with the SiO2 interlayer and Si substrate providing temperature compensation and thermal diffusion block, respectively. SAW device fabricated on the optimized LT/Si substrate shows a parabolic frequency–temperature relation with near zero temperature coefficient of frequency (TCF) in a low temperature range. SAW device fabricated on the novel LN/SiO2/Si substrate shows excellent performance with near constant TCF about −18 ppm/°C and electromechanical coupling coefficient ( $K^{2}$ ) near 18.69%. Theoretical analysis and performance comparison with reported works are presented to elucidate the temperature compensation mechanism of the proposed layered structures.

EMI resisting MOSFET-only voltage reference based on ZTC condition

Electromagnetic interference (EMI) can significantly degrades the performance of analog circuits, including voltage and current references, especially due to their limited power supply rejection. An EMI resistant MOSFET-only voltage reference is herein proposed, based on the MOSFET zero temperature coefficient (ZTC) vicinity condition. The ZTC condition is analytically derived through a continuous MOSFET model that is valid from weak to strong inversion, also a design methodology is presented. The final circuit is designed in a 130 nm process and occupies around 0.0075 mm$$^{2}$$2 of silicon area while consuming just 10.3 $$\upmu$$μW. Post-layout simulations present a 395 mV reference voltage ($$V_{REF}$$VREF) with a effective temperature coefficient ($$TC_{eff}$$TCeff) of 146 ppm/°C, for a temperature range from ź55 to +125 °C. A 4 dBm (1 $$V_{pp}$$Vpp amplitude) EMI source injected into the power supply, according to direct power injection standard [1], results in a maximum DC Shift and peak-to-peak ripple of ź1.7 % and 35.8 m$$V_{pp}$$Vpp, respectively. The proposed voltage reference has already been fabricated and is under preliminary measurements, presenting a maximum variation of 21 mV for a 600 mV minimum supply.

The investigation of the zero temperature coefficient point of power MOSFET

The paper investigates the zero temperature coefficient (ZTC) point of power MOSFET, based on the output characteristic of power MOSFET, the temperature coefficient of threshold voltage and the carrier mobility. It is found that the gate voltage has a big effect on the ZTC point. The result indicates that there are three types of temperature coefficient under different gate voltage. When the gate voltage is near the threshold voltage, both the linear region and saturation region shows a large positive temperature coefficient. With the increase of gate voltage, the temperature coefficient of the linear region changes from positive to negative, when the saturation region still remains positive, giving rise to the ZTC point. When the gate voltage is high enough, the negative temperature coefficient is present on both the linear and saturation region, resulting in no ZTC point. According to the experimental result, the change of ZTC point as a function of temperature is larger when the gate voltage is higher. The carrier mobility is also discussed, displaying a positive temperature coefficient at low gate voltage due to the free charge screen effect.

Evaluation of Acoustic Properties for Ca3Nb(Ga0.75Al0.25)3Si2O14 Single Crystal Using the Ultrasonic Microspectroscopy System.

Acoustically related physical constants were experimentally determined for Ca3Nb(Ga0.75Al0.25)3Si2O14 (CNGAS) single crystal for the first time. Several plate specimens of the X-, Y -, Z -, 40.24 ° Y -, and 144.98 ° Y -cut were prepared from a CNGAS single crystal ingot grown by Czochralski technique. Elastic constants, piezoelectric constants, and their temperature coefficients for CNGAS were determined from longitudinal wave and shear wave velocities at around room temperature, measured by the ultrasonic microspectroscopy system. Dielectric constants, density, and coefficients of thermal expansion were also measured. It was demonstrated that the determined constants could provide calculation accuracy within ±0.12% in leaky surface acoustic wave velocity. The piezoelectric constants for CNGAS were a 7.2% increase in e11 and a 1.7% decrease in e14 due to Al-substitution effect, compared with those of Ca3NbGa3Si2O14. The appropriate cut angle for thickness-shear mode resonator with zero temperature coefficient of velocity was estimated to be around 150 ° Y -cut from calculations using the determined constants of CNGAS exhibiting electromechanical coupling factor k2 of 3.19% and power flow angle of -1.70°.

Magnetic/structural phase diagram and zero temperature coefficient of resistivity in GaCFe3−xCox (0 ≤ x ≤ 3.0)

Magnetic/structural phase diagram of GaCFe3−xCox (0 ≤ x ≤ 3.0) were investigated systematically. It was found that the antiperovskite phase collapses at x = 0.90 and recovers again at x = 2.3 with Co doping. Along with this transformation, the ferromagnetic state in GaCFe3 is suppressed and replaced by the reentrant spin-glass state (2.3 ≤ x ≤ 2.6) or enhanced magnetic fluctuations (2.7 ≤ x ≤ 3.0). Ac susceptibility and magnetic relaxation were adopted to validate this spin-glass state for x = 2.5. It indicates that the contractive lattice as well as the resultant enhanced magnetic couplings may be an important origin of the collapsed antiperovskite structure. Zero temperature coefficient of resistivity (TCR) was achieved by Co-doping where the sign of TCR changes from positive to negative across the room temperature. The optimized TCR ∼ 0.0346 ppm/K spanning 110 K are three orders of magnitude smaller than those of CuNMn3 or GaCFe3. The physical mechanism was discussed.

Temperature dependency of double material gate oxide (DMGO) symmetric dual-k spacer (SDS) wavy FinFET

Symmetric Dual-k Spacer (SDS) Trigate Wavy FinFET is a novel hybrid device that combines three significant and advanced technologies i.e., ultra-thin-body (UTB), FinFET, and symmetric spacer engineering on a single silicon on insulator (SOI) platform. This innovative architecture promises to enhance the device performance as compared to conventional FinFET without increasing the chip area. For the first time, we have incorporated two different dielectric materials (SiO2, and HfO2) as gate oxide to analyze the effect on various performance metrics of SDS wavy FinFET. This work evaluates the response of double material gate oxide (DMGO) on parameters like mobility, on current (Ion), transconductance (gm), transconductance generation factor (TGF), total gate capacitance (Cgg), and cutoff frequency (fT) in SDS wavy FinFET. This work also reveals the presence of biasing point i.e., zero temperature coefficient (ZTC) bias point. The ZTC bias point is that point where the device parameters become independent of temperature. The impact of operating temperature (T) on above said various performances are also subjected to extensive analysis. This further validates the reliability of DMGO-SDS FinFET and its application opportunities involved in modeling analog/RF circuits for a broad range of temperature applications. From extensive 3-D device simulation, we have determined that the inclusion of DMGO in SDS wavy FinFET is superior in performance.

Relation between the residual induction and the temperature stability of sintered Nd–Dy–Fe–Co–B magnets

Relation between the temperature coefficient of induction of materials of the Nd–Dy–Fe–Co–B system at temperatures of 20–100°C and their residual induction has been found. It is shown that the residual induction is 0.6 T at the zero temperature coefficient of induction.

Reliability analysis of charge plasma based double material gate oxide (DMGO) SiGe-on-insulator (SGOI) MOSFET

A novel device named charge plasma based doping less double material gate oxide (DMGO) silicon–germanium on insulator (SGOI) double gate (DG) MOSFET is proposed for the first time. The fundamental objective in this work is to modify the channel potential, electric field and electron velocity for improving leakage current, transconductance (gm) and transconductance generation factor (TGF). Using 2-D simulation, we exhibit that the DMGO-SGOI MOSFET shows higher electron velocity at source side and lower electric field at drain side as compare to ultra-thin body (UTB) DG MOSFET. On the other hand DMGO-SGOI MOSFET demonstrates a significant improvement in gm and TGF in comparison to UTB-DG MOSFET. This work also evaluates the existence of a biasing point i.e. zero temperature coefficient (ZTC) bias point, where the device parameters become independent of temperature. The impact of operating temperature (T) on above said various performance metrics are also subjected to extensive analysis. This further validates the reliability of charge plasma DMGO SGOI MOSFET and its application opportunities involved in designing analog/RF circuits for a wide range of temperature applications.

ZTC bias point of advanced fin based device: The importance and exploration

The present understanding of this work is about to evaluate and resolve the temperature compensation point (TCP) or zero temperature coefficient (ZTC) point for a sub-20 nm FinFET. The sensitivity of geometry parameters on assorted performances of Fin based device and its reliability over ample range of temperatures i.e. 25?C to 225?C is reviewed to extend the benchmark of device scalability. The impact of fin height (HFin), fin width (WFin), and temperature (T) on immense performance metrics including on-off ratio (Ion/Ioff), transconductance (gm), gain (AV), cut-off frequency (fT), static power dissipation (PD), energy (E), energy delay product (EDP), and sweet spot (gmfT/ID) of the FinFET is successfully carried out by commercially available TCAD simulator SentaurusTM from Synopsis Inc.

Smart conducting polymer composites having zero temperature coefficient of resistance

Zero temperature coefficient of resistance (TCR) is essential for the precise control of temperature in heating element and sensor applications. Many studies have focused on developing zero-TCR systems with inorganic compounds; however, very few have dealt with developing zero-TCR systems with polymeric materials. Composite systems with a polymer matrix and a conducting filler show either a negative (NTC) or a positive temperature coefficient (PTC) of resistance, depending on several factors, e.g., the polymer nature and the filler shape. In this study, we developed a hybrid conducting zero-TCR composite having self-heating properties for thermal stability and reliable temperature control. The bi-layer composites consisted of a carbon nanotube (CNT)-based layer having an NTC of resistance and a carbon black (CB)-based layer having a PTC of resistance which was in direct contact with electrodes to stabilize the electrical resistance change during electric Joule heating. The composite showed nearly constant resistance values with less than 2% deviation of the normalized resistance until 200 °C. The CB layer worked both as a buffer and as a distributor layer against the current flow from an applied voltage. This behavior, which was confirmed both experimentally and theoretically, has been rarely reported for polymer-based composite systems.