XNOR Operations Research Articles

High-fidelity decryption technology for visual cryptography based on incoherent optical polarization XNOR operation

In this paper, we propose an optical high-fidelity decryption technology for Visual Cryptography (VC) based on incoherent optical polarization exclusive NOR (XNOR) operation. The plaintext image is divided into two binary ciphertexts by the Random-Grid-based Visual Secret Sharing (RGVSS) algorithm. These ciphertexts are printed onto the polarizing films with orthogonal polarization. The P- and S-polarizing pixels in the polarizing films represent the “black” and “white” pixels of the ciphertexts, respectively. Due to the optical transmission property of polarizing film, the pixel in the decrypted image appears bright only when the stacked pixels for the two ciphertexts have the same polarizing orientation. High-fidelity image decryption is then achieved. The proposed technology has been successfully demonstrated through simulation and experimentation. Thanks to its advantages of no pixel expansion, incoherent illumination, being free of computer assistance, and flexibility of ciphertext carriers, this method provides a broad prospect for convenient, large-format, high-fidelity information recovery applications for VC.

A 28-nm 9T SRAM-based CIM macro with capacitance weighting module and redundant array-assisted ADC

In the emerging field of Computing-in-Memory (CIM), this study introduces a 28-nm CMOS-based Static Random Access Memory (SRAM) CIM macro capable of various computational modes, potentially offering a solution to the Von Neumann bottleneck. Beyond traditional SRAM read and write operations, to enhance the flexibility of the CIM macro, a 9T cell is proposed for performing AND, OR, and XNOR operations; a new capacitive weighting module is introduced to reduce the area of conventional ladder capacitors; and a redundant array-assisted Analog-to-Digital Converter (ADC) is proposed to improve linearity during ADC quantization. The proposed architecture can achieve multi-bit multiplication and accumulation (MAC), OR accumulation (ORA), and XNOR accumulation (XNORA). Simulated using a 28-nm CMOS process, the architecture demonstrated a minor standard deviation in BL voltage of 16.27 mV at the SS process corner, as evidenced by Monte Carlo simulation. At the TT process corner, the energy expenditure for MAC, XNORA, and ORA operations was 5.76, 5.85, and 5.82 fJ/op, respectively.

A Reconfigurable Ferroelectric Transistor as An Ultra‐Scaled Cell for Low‐Power In‐Memory Data Processing

AbstractCompact in‐memory computing architectures are desirable to embed artificial intelligence (AI) in resource‐restricted edge devices. However, current technologies face limitations in both the area and energy efficiency. Here, a reconfigurable ferroelectric tunnel field‐effect transistor (ferro‐TFET) is presented that can be used as an ultra‐scaled cell for low‐power in‐memory data processing. A gate‐all‐around ferroelectric film is integrated on a vertical nanowire TFET with a gate/source overlapped channel, enabling non‐volatilely reconfigurable anti‐ambipolarity by programming the ferroelectric polarization state. By considering the stored polarization state and reading voltage as inputs, an XNOR operation is achieved in a single‐gate ferro‐TFET. It is shown that the ferro‐TFETs can be implemented in a crossbar array for convolutional frequency filtering whose performance can be evaluated by an impulse‐response method considering the effect of device‐to‐device variation based on statistics. Benefiting from the miniaturized footprint, non‐volatility, and low‐power operation, ferro‐TFETs show promises as a one‐transistor in‐memory computing cell for area‐ and energy‐efficient edge AI applications.

Solving System of Mixed Ordered Variational Inequalities Involving XOR and XNOR Operations in Ordered Product Banach Space

In this article, we study a generalized system of mixed ordered variational inequalities problems with various operations in a real ordered product Banach space and discuss the existence of the solution of our considered problem. Further, we discuss the convergence analysis of the proposed iterative algorithm using XNOR and XOR operations techniques. Most of the variational inequalities solved by the projection operator technique but we solved our considered problem without the projection technique. The results of this paper are more general and new than others in this direction. Finally, we give a numerical example to illustrate and show the convergence of the proposed algorithm in support of our main result has been formulated by using MATLAB programming. 2010 AMS Subject Classification: 47H09; 49J40.

Enhancing on/off ratio of a dielectric-loaded plasmonic logic gate with an amplitude modulator

Plasmonic waveguides allow focusing, guiding, and manipulating light at the nanoscale and promise the miniaturization of functional optical nanocircuits. Dielectric-loaded plasmonic (DLP) waveguides and logic gates have drawn attention because of their relatively low loss, easy fabrication, and good compatibility with gain and active tunable materials. However, the rather low on/off ratio of DLP logic gates remains the main challenge. Here, we introduce an amplitude modulator and theoretically demonstrate an enhanced on/off ratio of a DLP logic gate for XNOR operation. Multimode interference (MMI) in DLP waveguide is precisely calculated for the design of the logic gate. Multiplexing and power splitting at arbitrary multimode numbers have been theoretically analyzed with respect to the size of the amplitude modulator. An enhanced on/off ratio of 11.26 dB has been achieved. The proposed amplitude modulator can also be used to optimize the performance of other logic gates or MMI-based plasmonic functional devices.

Enabling Energy-Efficient In-Memory Computing With Robust Assist-Based Reconfigurable Sense Amplifier in SRAM Array

With the increasing gap between processing speed and memory bandwidth necessity for in/near-memory computing has emerged, to ensure high-performance, energy-efficient computing for data-intensive applications at the edge. This work proposes a feasible SRAM compute cache with a sense amplifier (SA) based approach to perform in-/near memory Boolean computations with a novel reconfigurable assist sense amplifier (RASA). The RASA exploits assist transistors to achieve NAND, NOR and XNOR operations without affecting the transparency of normal read leading to fast and reliable sensing with only one SA. This effectively eliminates the need for two SAs in comparison to state-of-the-art solutions. The proposed work improves memory density and reduces cost-per-bit by leveraging the SA-based approach because existing solutions lead to significant area overhead/cell which reflects overhead multiply by the number of cells/column. The RASA provides flexibility to accommodate more cells per column at the architecture level. Extensive Monte-Carlo analysis is performed to verify the feasibility of the proposed circuit in commercial 65nm UMC technology under iso-SA area and iso-yield conditions. Simulations indicate a 34.34%, 84.87%, 81.21%, 75.46% improvement in energy, and a 71.30%, 43.36%, 32.49%, 17.44% improvement in throughput leading to a reduction of 60.97%, 91.37%, 87.22%, 79.62% in energy-delay product with respect to CLSA (Dong et al., 2018), CSRAM (Chen et al., 2021), RRCSA (Rajput et al., 2022) and the ADSA (Agrawal et al., 2018) respectively. An improvement in the area of SA by 36.512% is achieved with respect to RRCSA.

Power and Area-Efficient XNOR-AND Hybrid Binary Neural Networks Using TFT-Type Synaptic Device

A novel XNOR- AND hybrid binary neural network (BNN) using a TFT-type synaptic device is proposed to reduce the area and power consumption of the synaptic array. Replacing some parts of the network from the XNOR operation to the AND operation results in expressing weight and input with a single cell and single word line. In the case of replacing the operation of the fully-connected (FC) layer with the AND operation, the accuracy of VGG9 BNN for CIFAR-10 datasets drops by about 1%, while the number of cells in the synaptic array decreases by 33.7%. Using the previously proposed TFT-type synaptic devices, the proposed method reduces power consumption by ~25%.

Quantum Color Image Encryption Scheme Based on Geometric Transformation and Intensity Channel Diffusion

A quantum color image encryption algorithm based on geometric transformation and intensity channel diffusion was designed. Firstly, a plaintext image was transformed into a quantum state form using the quantum image representation based on HSI color space (QIRHSI) representation as a carrier. Next, a pseudo-random sequence was generated using the generalized logistic map, and the pixel positions permuted multiple two-point swap operations. Immediately afterward, the intensity values were changed by an intensity bit-plane cross-swap and XOR, XNOR operations. Finally, the intensity channel of the above image was diffused in combination with the pseudo-confusion sequence as produced by the quantum logistic map to perform a diffusion operation on the intensity bit-plane to obtain the ciphertext image. Numerical simulations and analyses show that the designed algorithm is implementable and robust, especially in terms of outstanding performance and less computational complexity than classical algorithms in terms of security perspective.

MOL-Based In-Memory Computing of Binary Neural Networks

Convolutional neural networks (CNNs) have proven very effective in a variety of practical applications involving artificial intelligence (AI). However, the layer depth of CNN deepens as user applications become more sophisticated, resulting in a huge number of operations and increased memory size. The massive amount of the produced intermediate data leads to intensive data movement between memory and computing cores causing a real bottleneck. In-memory computing (IMC) aims to address this bottleneck by directly computing inside memory, eliminating energy-intensive and time-consuming data movement. On the other hand, the emerging binary neural networks (BNNs), which is a special case of CNN, show a number of hardware-friendly properties, including memory saving. In BNN, the costly floating-point multiply-and-accumulate is replaced with lightweight bitwise XNOR and popcount operations. In this article, we propose an IMC programmable architecture targeting efficient implementation of BNN. Computational memories based on the recently introduced memristor overwrite logic (MOL) design style are employed. The architecture, which is presented in semiparallel and parallel models, efficiently executes the advanced quantization algorithm of XNOR-Net BNN. Performance evaluation based on the CIFAR-10 dataset demonstrates between <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.24\times $ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$3\times $ </tex-math></inline-formula> speedup and 49% and 99% energy saving compared to state-of-the-art implementations and up to 273-image/s/W throughput efficiency.

Novel, parallel and differential synaptic architecture based on NAND flash memory for high-density and highly-reliable binary neural networks

A novel synaptic architecture based on a NAND flash memory structure is proposed as a high-density synapse capable of exclusive NOR (XNOR) operation for binary neural networks (BNNs). For the first time, a 4T2S-based synaptic architecture with a complementary input voltage that implements an equivalent bitwise XNOR operation is proposed. Two adjacent NAND flash strings connected with the word lines are used as one synaptic string with four input transistors connected to the bit-line. By changing the threshold voltage of the NAND flash cells and input voltages in a complementary fashion, the XNOR operation is successfully demonstrated. The large on/off current ratio (∼7 × 105) of the NAND flash cells and differential sensing scheme can implement high-density and highly reliable binary neural networks without error correcting codes (ECC), which can reduce the burden of the complementary metal–oxide–semiconductor (CMOS) overhead. Despite the string structure of NAND flash memory, the parallel read scheme significantly reduces the read-out latency when compared to the sequential read scheme. In addition, we show that with only 1 erase/program pulse, sufficiently low bit-error rate (7.6 × 10−9 %) is achieved without the conventional incremental step pulse programming (ISPP) scheme. Finally, the estimated synapse density of V-NAND flash memory with 128 stacks is ∼103 times that of the 2T2R synapse in resistive random access memory (RRAM).

A BNN Accelerator Based on Edge-skip-calculation Strategy and Consolidation Compressed Tree

Binarized neural networks (BNNs) and batch normalization (BN) have already become typical techniques in artificial intelligence today. Unfortunately, the massive accumulation and multiplication in BNN models bring challenges to field-programmable gate array (FPGA) implementations, because complex arithmetics in BN consume too much computing resources. To relax FPGA resource limitations and speed up the computing process, we propose a BNN accelerator architecture based on consolidation compressed tree scheme by combining both XNOR and accumulation operation of the low bit into a systematic one. During the compression process, we adopt 0-padding (not ±1) to achieve no-accuracy-loss from software modeling to hardware implementation. Moreover, we introduce shift-addition-BN free binarization technique to shorten the delay path and optimize on-chip storage. To sum up, we drastically cut down the hardware consumption while maintaining great speed performance with the same model complexity as the previous design. We evaluate our accelerator on MNIST and CIFAR-10 dataset and implement the whole system on the ARTIX-7 100T FPGA with speed performance of 2052.65 GOP/s and area efficiency of 70.15 GOPS/KLUT.

A New Blended Approach of Data Hiding Using XNOR Operation

This paper proposed a new data hiding technique which uses a blended approach of security. It uses a blend of cryptography and steganography at the same time to provide two layers of security. At first, data is encrypted using Rail Fence cryptography algorithm and at the second level the encrypted data is inserted into an image by using insertion algorithm based on XNOR operation. Encrypted bits are put into the pixels of the image which becomes a difficult task for the attackers to find the hidden data. In this approach, the concept of spatial domain is used for hiding the message and retrieval of message. The preliminary experimental results based on PSNR, MSE, Histogram and Coefficient of Correlation show that the proposed method provides better imperceptibility and hiding capacity. It was also compared with some trade off methods on the basis of various metrics. It also provides very less deflection in cover image so that it becomes very difficult for a third person to differentiate between cover image and stego image. ImageData HidingSteganographyCryptography

Fast and Robust Image Encryption Scheme Based on Quantum Logistic Map and Hyperchaotic System

Topic of quantum chaos has begun to draw increasing attention in recent years. So, to ensure the security of digital image, an image encryption algorithm based on combining a hyperchaotic system and quantum 3D logistic map is proposed. This algorithm is applied in four stages. Initially, the key generator builds upon the foundation of mean for any row or column of the edges of the plain image. Its output value is used to yield initial conditions and parameters of the proposed image encryption scheme. Next, it diffuses the plain image by the random sequences generated by 3D hyperchaotic system, and the diffusion process is realized by implementing XOR operation. Then, the diffused image and chaotic sequences are produced by the 3D quantum chaotic logistic map, expressed as a quantum superposition state using density matrix which is a representation of the state of a quantum system, and finally the resulting quantum image is then confused and diffused simultaneously by a unitary matrix generated by logistic chaos using XNOR operation to obtain the final cipher image. Because of the dependence on the plain image, the algorithm can frustrate the chosen‐plaintext and known‐plaintext attacks. Simulation results and theoretical analysis verify that the presented scheme has high safety performance, a good encryption effect, and a large key space. The method can effectively resist exhaustive, statistical, and differential attacks. Moreover, the encryption time of the proposed method is satisfactory, and the method can be efficiently used in practice for the secure transmission of image information.

SiO2 Fin-Based Flash Synaptic Cells in AND Array Architecture for Binary Neural Networks

An oxide fin-based AND flash memory synaptic device is proposed and fabricated using a spacer patterning technology for a hardware-based binary neural network (BNN). A fin-like curved channel structure provides local electric field enhancement, which improves programming efficiency compared to planar-type flash synaptic devices. The fin-based AND flash cell exhibits a high on/off current ratio (>10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">5</sup> ) with sub-pA off current, and a low programming voltage (< 9 V) is used to achieve a sufficient dynamic range of synaptic weights (>10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sup> ) for BNNs. Furthermore, a hardware-based BNN using novel two cell-based synaptic devices arranged in AND array architecture is proposed to implement parallel XNOR operation and bit-counting. Proposed BNN using the synapse model with measured dynamic range and retention property shows only < 0.5 % degradation of classification accuracy compared to the baseline accuracy, which is suitable to perform off-chip event-driven computation using parallel read-out operations.

An adiabatic method to train binarized artificial neural networks

An artificial neural network consists of neurons and synapses. Neuron gives output based on its input according to non-linear activation functions such as the Sigmoid, Hyperbolic Tangent (Tanh), or Rectified Linear Unit (ReLU) functions, etc.. Synapses connect the neuron outputs to their inputs with tunable real-valued weights. The most resource-demanding operations in realizing such neural networks are the multiplication and accumulate (MAC) operations that compute the dot product between real-valued outputs from neurons and the synapses weights. The efficiency of neural networks can be drastically enhanced if the neuron outputs and/or the weights can be trained to take binary values pm 1 only, for which the MAC can be replaced by the simple XNOR operations. In this paper, we demonstrate an adiabatic training method that can binarize the fully-connected neural networks and the convolutional neural networks without modifying the network structure and size. This adiabatic training method only requires very minimal changes in training algorithms, and is tested in the following four tasks: the recognition of hand-writing numbers using a usual fully-connected network, the cat-dog recognition and the audio recognition using convolutional neural networks, the image recognition with 10 classes (CIFAR-10) using ResNet-20 and VGG-Small networks. In all tasks, the performance of the binary neural networks trained by the adiabatic method are almost identical to the networks trained using the conventional ReLU or Sigmoid activations with real-valued activations and weights. This adiabatic method can be easily applied to binarize different types of networks, and will increase the computational efficiency considerably and greatly simplify the deployment of neural networks.

Experimental demonstration of a broadband optoelectronic chaos system based on highly nonlinear configuration of IQ modulator.

We experimentally investigated a novel broadband optoelectronic chaos generation scheme. The proposed system is achieved by adopting the highly nonlinear operation of an electro-optical exclusive-NOR (XNOR) logic gate and two delayed feedback loops that refer to the Boolean chaos model. The XNOR gate is established by a commercial use inphase and quadrature-phase (IQ) modulator that works at a specific bias point. The resulting power spectrum of the broadband chaos signal extends from DC to 29.1 GHz (10 dB bandwidth), and the probability density distribution is Gaussian distribution like. Owing to the strong nonlinearity of XNOR operation, the conditions to enter the chaos region are more relaxed compared to traditional optoelectronic oscillator (OEO) chaos systems, and the time delay signature (TDS) of the feedback loop is also suppressed. Moreover, to further enhance the performance of the generated chaos signal, we injected the optoelectronic chaotic signal into a semiconductor laser. Experimental results indicate that after the cascade optical injection, the bandwidth of the output chaos signal is extended to 38.4 GHz and the TDS is completely concealed; meanwhile, a perfect Gaussian distribution can be obtained.

Three-step Iterative Algorithm with Error Terms of Convergence and Stability Analysis for New NOMVIP in Ordered Banach Spaces

This article undertakes to study a NOMVIP involving XNOR-operation and solved by employing a proposed three-step iterative algorithm in ordered Banach Space. Under suitable conditions, we obtain the strong convergence and existence results of NOMVIP involving XNOR-operation by applying the resolvent operator technique with XNOR and XOR operations and discuss the stability of the proposed algorithm. Finally, we provide a numerical example to confirm the convergence of the suggested algorithm in support of our considered problem which gives the grantee that all the proposed conditions of our main result have been formulated by using MATLAB programming.

Energy-Efficient All-Spin BNN Using Voltage-Controlled Spin-Orbit Torque Device for Digit Recognition

Artificial intelligence has been demonstrated for numerous applications including image recognition and processing, internet-of-things (IoT), and speech recognition. Recent neural network (NN) architectures escalating to perform these functionalities require deep-learning and deep NN (DNN) implementation. However, the present algorithm and circuit of DNN suffer from area and energy-efficiency. The usage of an energy-efficient and cost-effective binary NN (BNN) can mitigate the performance bottleneck. The basic component of BNN (the XNOR and accumulate module) is capable of replacing the conventional multiply-and-accumulate (MAC) operation. Among various emerging nonvolatile memories (NVMs), spintronics-based devices are attracting attention for the implementation of the aforementioned architectures. Multilevel voltage-controlled spin-orbit torque -based magnetic memory (MV-SOTM) spin device as synapse and voltage-controlled SOTM (V-SOTM) device as spin-neuron are capable of producing an all-spin NN. This article presents advanced XNOR operation using a computing-in-memory (CiM) mechanism wherein both V-SOTM and MV-SOTM (using series and parallel configuration) based synapses are compared. The MV-SOTM design dissipates 35.51% lesser energy as compared to the 1-bit V-SOTM. Further, the 8-bit synaptic crossbar array is implemented using both the devices with two output spin-neurons. These series and parallel MV-SOTM-based synaptic arrays consume 42.22% and 45.12% lesser power, respectively, as compared to 1-bit V-SOTM based synaptic array. Furthermore, the all-spin BNN design demonstrates a handwritten digit recognition application.

Hybrid Pass Transistor Logic With Ambipolar Transistors

In comparison to the conventional complementary pull-up and pull-down logic structure, the pass transistor logic (PTL) family reduces the number of transistors required to perform logic functions, thereby reducing both area and power consumption. However, this logic family requires inter-stage inverters to ensure signal integrity in cascaded logic circuits, and inverters must be used to provide each logical input signal in its complementary form. These inverters and complementary signals increase the device count and significantly degrade overall system efficiency. Dual-gate ambipolar field-effect transistors natively provide a single-transistor XNOR operation and permit highly-efficient and compact circuits due to their ambipolar capabilities. Similar to PTL, logic circuits based on ambipolar field-effect transistors require complementary signals. Therefore, numerous inverters are required, with significant energy and area costs. Ambipolar field-effect transistors are a natural match for PTL, as hybrid ambipolar-PTL circuits can simultaneously use these inverters to satisfy their necessity in both PTL and ambipolar circuits. We therefore propose a new hybrid ambipolar-PTL logic family that exploits the compact logic of PTL and the ambipolar capabilities of ambipolar field-effect transistors. Novel hybrid ambipolar-PTL circuits were designed and simulated in SPICE, demonstrating strong signal integrity along with the efficiency advantages of using the required inverters to simultaneously satisfy the requirements of PTL and ambipolar circuits. In comparison to the ambipolar field-effect transistors in the conventional CMOS logic structure, our hybrid full adder circuit can reduce propagation delay by 47%, energy consumption by 88%, energy-delay product by a factor of 9, and area-energy-delay product by a factor of 20.

A Monolithic 3-D Integration of RRAM Array and Oxide Semiconductor FET for In-Memory Computing in 3-D Neural Network

We have monolithically integrated resistance random access memory (RRAM) array with oxide semiconductor channel access transistor in 3-D stack, achieved uniform memory characteristics of 1T1R cells at each layer, and demonstrated basic functionality of XNOR operation as in-memory computing for binary neural network (BNN) artificial intelligence (AI) applications. The integrated TiN/Ti/HfO2/Ti stack RRAM shows high on/off ratio with stable retention and endurance properties. The indium gallium zinc oxide (IGZO) channel field-effect transistor (FET) works as an access transistor, which realized the low-temperature process, high mobility, and high drive current for RRAM. With the peripheral circuit, we demonstrate the XNOR operation using a pair of 1T1R cells. The impact of RRAM bit error rate on neural network is also investigated, which indicates the property of error-resilience in BNN. The 3-D neural network built by this architecture has high potential to enable area-efficient, low-power, and low-latency computing.