Xilinx Virtex-5 FPGA Research Articles

FPGA Based Optimized Reconfigurable Base-2 Constant Coefficient Multiplier Architecture for Image Filtering

Image convolution using FPGA has been comprehensively used for noise removal of Reconfigurable computing based image Processing Algorithm. Particularly these filters are widely used in embedded computer vision applications like edge detection and Feature extraction analysis. Practical implementation of filter requires enormous computational requirement. The multiplier plays very important role in the image convolution. The existed multiplier design requires more computational complexity for the 3x3 test image. For this the proposed reconfigurable constant coefficient multiplier uses base-2 Common sub expression algorithm. which reduces the computational complexity in a better way. The proposed 2D-convolution in image application is the value of resultant output is multiplication of image pixel with corresponding kernel value. In this work the realization of 2D convolution to be done using proposed constant coefficient multiplier and analyzed using Xilinx Virtex-5 FPGA platform

Implementation of Dormand-Prince based chaotic oscillator designs in different IQ-Math number standards on FPGA

Chaos and chaotic systems, one of the most important work areas in recent years, are used in areas such as cryptology and secure communication, industrial control, artificial neural networks, random number generators and image processing. The most basic structure used in these studies is a chaotic oscillator design that produces a chaotic signal. Chaotic oscillators are expressed by using differential equations. Numerical algorithms such as Euler, Heun, fourth order Runge-Kutta-4 (RK4), fifth order RK5-Butcher and Dormand-Prince are used for solving these differential equations. When the current literature is searched, chaotic oscillator designs are found by Euler, Heun, RK4 and RK5- Butcher method. However, FPGA-based chaotic oscillator design studies have not been found using the Dormand-Prince method, which produces more accurate solutions than other methods. In this work, self-excited attractor chaotic system was first designed in 16I-16Q, 14I-14Q, 12I-12Q, 10I_10Q, 8I-8Q IQ-Math number standards on FPGA using Dormand-Prince numerical algorithm and encoded in VHDL language. Xilinx ISE Design Tools were used to design the chaotic system. The design was synthesized and tested for the Xilinx Virtex-6 FPGA chip. Using the Xilinx ISE design tool, the chip statistics and maximum operating frequency obtained after the "Route-Place" operation are presented. In future work, safe communication and real random number generator applications can be realized by using the Dormand-Prince based oscillator design presented in this study.

Multi-depth filtering and occlusion suppression in 4-D light fields: Algorithms and architectures

Low-complexity signal processing algorithms and reconfigurable digital hardware architectures are proposed for multi-depth filtering and occlusion suppression in 4-D light fields (LFs). The proposed multi-depth-pass (MDP) and multi-depth-reject (MDR) 4-D filters allow simultaneous enhancement of planar objects at multiple desired depths and attenuation of planar objects at multiple undesired depths, thereby achieving electronically tunable multi-depth focusing. Partial-separability and recursive nature of the proposed MDP and MDR transfer functions ensure ultra-low hardware complexity suitable for real-time processing of large volume of input samples encountered in 4-D LFs. Filter synthesis details and examples with synthetic and real LFs of size 15 × 15 × 434 × 625 are presented. A generic framework encapsulating a multitude of possible digital hardware realizations is described, employing J-unfolding and look-ahead pipelining albeit with modifications as applicable to the underlying multi-dimensional signal flow graphs to obtain increased real-time throughput. Proof-of-concept digital designs are provided for the 2-passband case of a MDP filter verifying a real-time throughput of ≈ 490 LFs of size 9 × 9 × 434 × 625 per second for filters operating at 135 MHz on a Xilinx Virtex-7 FPGA device.

High Speed Parallel SAD Architecture Implementation on FPGA for HEVC encoder

Video compression is a very complex and time consuming task which generally pursuit high performance. Motion Estimation (ME) process in any video encoder is responsible to primarily achieve the colossal performance which contributes to significant compression gain. Summation of Absolute Difference (SAD) is widely applied as distortion metric for ME process. With the increase in block size to 64×64 for real time applications along with the introduction of asymmetric mode motion partitioning(AMP) in High Efficiency Video Encoding (HEVC)causes variable block size motion estimation very convoluted. This results in increase in computational time and demands for significant requirement of hardware resources. In this paper parallel SAD hardware circuit for ME process in HEVC is propound where parallelism is used at various levels. The propound circuit has been implemented using Xilinx Virtex-5 FPGA for XC5VLX20T family. Synthesis results shows that the propound circuit provides significant reduction in delay and increase in frequency in comparison with results of other parallel architectures

High Performance Matrix Multiplication based on Xilinx Virtex FPGA

High Performance Matrix Multiplication based on Xilinx Virtex FPGA

An Efficient Hardware Implementation of Finite Field Inversion for Elliptic Curve Cryptography

The modular inversion operation is an essential hardware design for computing speed when we use it in cryptography applications. Through this work, we present a FSM based design methodology to achieve speed, area and high-performance modular binary inversion algorithm over 256-bit prime field. The proposed architecture implemented using Xilinx Virtex-7 FPGA device, it achieves 37% reduction in area-delay product and 15% and 16% of improvement in speed and throughput respectively, when compared with existing designs. Also, ASIC based implementation is done using TSMC 65nm CMOS technology, the synthesis results achieved the maximum operating clock frequency is 833 MHz and throughput of 626Mbps, which makes it suitable for speed-critical cryptoapplications.

Compact and high‐throughput parameterisable architectures for memory‐based FFT algorithms

Designers must carefully choose the best-suited fast Fourier transform (FFT) algorithm among various available techniques for the custom implementation that meets their design requirements, such as throughput, latency, and area. This article, to the best of authors' knowledge, is the first to present a compact and yet high-throughput parameterisable hardware architecture for implementing different FFT algorithms, including radix-2, radix-4, radix-8, mixed-radix, and split-radix algorithms. The designed architectures are fully parameterisable to support a variety of transform lengths and variable word-lengths. The FFT algorithms have been modelled and simulated in double-precision floating-point and fixed-point representations using authors' custom-developed library of numerical operations. The designed FFT architectures are modelled in Verilog hardware description language and their cycle-accurate and bit-true simulation results are verified against their fixed-point simulation models. The characteristics and implementation results of various FFT architectures on a Xilinx Virtex-7 FPGA are presented. Compared to recently published works, authors' memory-based FFT architectures utilise less reconfigurable resources while maintaining comparable or higher operating frequencies. The ASIC implementation results in a standard 45-nm CMOS technology are also presented for the designed memory-based FFT architectures. The execution times of FFTs on a workstation and a graphics processing unit are compared against authors' FPGA implementations.

A Hybrid Countermeasure-Based Fault-Resistant AES Implementation

A Fault-Resistant scheme has been proposed to secure the Advanced Encryption Standard (AES) against Differential Fault Analysis (DFA) attack. In this paper, a hybrid countermeasure has been presented in order to protect a 32-bits AES architecture proposed for resource-constrained embedded systems. A comparative study between the most well-known fault detection schemes in terms of fault detection capabilities and implementation cost has been proposed. Based on this study, we propose a hybrid fault resistant scheme to secure the AES using the parity detection for linear operations and the time redundancy for SubBytes operation. The proposed scheme is implemented on the Virtex-5 Xilinx FPGA board in order to evaluate the efficiency of the proposed fault-resistant scheme in terms of area, time costs and fault coverage (FC). Experimental results prove that the countermeasure achieves a FC with about 98,82% of the injected faults detected during the 32-bits AES process. The area overhead of the proposed countermeasure is about 14% and the additional time delay is about 13%.

Design and Implementation of 5-D IIR Depth Velocity Filters for Light Field Video Processing

The design and hardware implementation of a low-complexity signal processing algorithm is proposed for real-time depth-velocity filtering in 5-D light field videos (LFVs). The proposed design is based on a stable 5-D infinite impulse response digital filter having three cascaded sections, each synthesized using the concept of multidimensional passive network resonance. A novel semi-systolic hardware implementation is proposed. Each section of the filter is implemented and tested on a Xilinx Virtex-7 FPGA platform using MATLAB-based hardware co-simulation with both synthetic and real LFV signals. A real-time processing throughput of 467 LFV frames/s is implied with each section of the filter operating at 204, 164, and 115 MHz for input LFV frames of size $9 \times 9 \times 220 \times 360$ .

Toward data-driven architectural support in improving the performance of future HPC architectures

We propose architectures based on Data-Driven Multithreading (DDM), a hybrid control-flow/data-flow model, to address the concurrency challenges faced by future High-Performance Computing (HPC) systems. We focus on the design and implementation of an optimized hardware Thread Scheduling Unit (TSU) and its integration into a multi-core system dubbed MiDAS. The TSU is the core of the DDM model and it orchestrates the execution of multiple threads on sequential processors based on data availability. MiDAS was prototyped on a Xilinx Virtex-6 FPGA and extensively evaluated using several micro-benchmarks, showing that it achieves linearly-growing performance as the processing core count increases even when running benchmarks comprising very small problem sizes. Under the largest problem size tested and with all 8 available cores being utilized, MiDAS achieves an average speedup of 7.91×, exhibiting 98.8% utilization efficiency. Further, several results pertaining to the proposed hardware TSU are provided, including FPGA real estate requirements, where it is found that MiDAS’s TSU demands relatively small overheads and reduced power consumption, while various TSU operations adhere to low latency responses. To back said claims, the proposed DDM-based TSU is compared with the Task Superscalar architecture that implements the StarSs programming framework in hardware. As such, comparison results show that the proposed TSU requires much less of both hardware investment and energy consumption to operate. Specifically, Task Superscalar is found to be 4.94 × larger than the DDM-supporting TSU in terms of slice register requirements and 11.34 × larger with respect to the slice look-up table count. Last, the hardware TSU is compared with a software TSU implementation offering identical functionalities, with both being run on an FPGA fabric under a synthetic application, where a detailed performance evaluation shows that MiDAS’s hardware-implemented TSU significantly outperforms its software-based TSU counterpart.

An FPGA design and implementation of EPZS motion estimation algorithm for 3D H.264/MVC standard

In the Three-Dimensional H.264 Multi-view Video Coding (3D H.264/MVC), the original 3D Video (3DV) sequence is a combination of variable video frames captured for the same object by different cameras. Therefore, in order to transmit 3DV content over limited-resources networks, a highly-efficient compression mechanism must be applied, while achieving a better reception quality. Moreover, in real-time applications such as 3DV conference and streaming, it is mandatory that the process of 3DV compression/decompression is speedy. Because it is known that most of the design complexity of the utilized 3D H.264/MVC codec come from the encoder part not from the decoder part, where the Motion Estimation (ME) process presents the highest computational complexity. In this work, an efficient implementation of the Enhanced Predictive Zonal Search (EPZS) ME algorithm is introduced for the 3D H.264/MVC standard. The EPZS algorithm is one of the most common and best ME algorithms. The overall inter-frame and inter-view prediction mechanisms including Motion Compensation (MC) and ME have been implemented. For validation and comparative analysis purposes, the outcomes of the suggested 3DV design for the EPZS ME algorithm are contrasted to more state-of-the-art ME algorithms. The suggested architecture of the EPZS ME algorithm is implemented in VHDL, synthesized utilizing Xilinx Virtex-6 FPGA and Xilinx ISE Design Suite 13.3, simulated employing ModelSim SE 6.5, and validated utilizing MATLAB SIMULINK. Experimental results prove that the suggested architecture achieves a low hardware complexity implementation and high-speed of 3D H.264/MVC compression process. This can be exploited for the utilization of the proposed work for real-time 3DV applications.

High-Speed ECC Processor Over NIST Prime Fields Applied With Toom–Cook Multiplication

In this paper, a high-speed elliptic curve cryptography (ECC) processor specialized for primes recommended by the National Institute of Standards and Technology (NIST) was constructed. Toom–Cook multiplication without division was proposed to implement modular multiplication for NIST primes. Compared with a traditional algorithm, the computation complexity was reduced from 16 base multiplications to 7 in 4-way Toom–Cook multiplication. Moreover, we introduced non-least-positive (NLP) form into our design, so that the carry chain in the large array accumulation was broken down, which greatly shortened the critical path and made parallel processing possible. In order to support NLP form and lazy reduction strategy, conventional fast reduction methods for NIST primes were also modified. In addition, pipeline technique at the level of point multiplication was used, so the latency of modular inverse can be covered. Implemented on the Xilinx Virtex-6 FPGA platform, the ECC processor can perform a point multiplication every 54 $\mu s$ at the cost of 30.3k LUTs and 48 DSPs. Synthesized with 180nm CMOS technology, the speed achieves 43.7 $\mu s$ with 466k gate counts. These experimental results show a significantly better performance per area than previous works.

A Massively Parallel Implementation of a Modular Self-Organizing Map on FPGAs

This paper describes the architecture design of novel massively parallel self-organizing map (SOM) neural networks. The proposed architecture, referred to as the planar SOM (PSOM), is described as a soft IP core synthesized in VHDL. The SOM neural network’s size and the input data vectors’ dimension are adjustable parameters. In this work, several SOM architectures are synthesized and their performance is evaluated for Xilinx Virtex-7 FPGAs. The presented hardware architecture allows online learning and can be easily adapted to a large variety of SOM topologies without a considerable design effort. A [Formula: see text] SOM hardware is validated through the FPGA implementation and its performances with an estimated working frequency of 297[Formula: see text]MHz for a 23-element input vector will reach 21,970 MCUPS in the learning phase and 35,902 MCPS in the recall one.

Speed-Oriented Architecture for Binary Field Point Multiplication on Elliptic Curves

This paper introduces a novel speed-oriented architecture of point multiplication in elliptic curve cryptography. A balanced full-precision multiplier is proposed to shorten latency, and a new modular inversion architecture is integrated to reduce the total number of clock cycles in point multiplication. A modified Montgomery Ladder algorithm that takes three clock cycles to calculate one input bit is proposed to best utilize hardware resources. A mixed-pipeline technique is used to balance the delay of different paths and increase frequency. The proposed architecture is implemented on GF(2163) and GF(2571), based on Xilinx Virtex-5 and Virtex-7 FPGA. For GF(2163), the design reaches 211 MHz, with 29309 LUTs, and 547 clock cycles or $2.6~\mu \text{s}$ latency on Virtex-5; 320.5 MHz, with 28911 LUTs and $1.7~\mu \text{s}$ latency on Virtex-7. For GF(2571), the design reaches 186 MHz, with 286400 LUTs, and 1813 clock cycles or $9.6~\mu \text{s}$ latency on Virtex-5; 267 MHz, 290001 LUTs and $6.79~\mu \text{s}$ latency on Virtex-7. The proposed design achieves the lowest latency among all existing works, and its performance is also among the top. Furthermore, it is demonstrated that the proposed architecture maintains a high speed for larger binary fields, making it more suitable to be implemented in large-bit-length platforms with a higher security level. Since the multiplier and its segments work in different bit-length and refer to different fields, the proposed architecture can also be upgraded to a reconfigurable design to support multiple-field point multiplication in the future.

High-performance ECC processor architecture design for IoT security applications

In recent years, the usage of elliptic curve cryptography (ECC) in IoT applications is steadily increasing. The end nodes in IoT applications demand optimized device performance in terms of reduced power consumption and improved computing speed while not compromising on the security of the connected devices. ECC provides better security standards compared with many conventional cryptographic algorithms providing further scope to optimize the performance parameters. This work focuses on improving the key parameters like computing speed, area required for hardware implementation of ECC and demonstrates an efficient way of using the hardware resource sharing and scheduling mechanisms in elliptic curve group operations in affine coordinates which is crucial for implementation of scalar multiplication over prime field $$\mathbb {F}_{p}$$ . With the proposed scalar multiplication hardware architecture, we have achieved a good area-delay product and a significant reduction in cycle count when compared with other reported designs using the same affine coordinates. The proposed architecture has been implemented with 256 bits in both Xilinx Kintex-7 and Virtex-7 FPGA devices. The FPGA synthesis results show that a throughput of 68.52 kbps at a clock frequency of 124.2 MHz is achieved for $$\mathbb {F}_{256}$$ and the computation time is reduced around 1 ms without using any DSP slices.

Less Data Same Information for Event-Based Sensors: A Bioinspired Filtering and Data Reduction Algorithm.

Sensors provide data which need to be processed after acquisition to remove noise and extract relevant information. When the sensor is a network node and acquired data are to be transmitted to other nodes (e.g., through Ethernet), the amount of generated data from multiple nodes can overload the communication channel. The reduction of generated data implies the possibility of lower hardware requirements and less power consumption for the hardware devices. This work proposes a filtering algorithm (LDSI—Less Data Same Information) which reduces the generated data from event-based sensors without loss of relevant information. It is a bioinspired filter, i.e., event data are processed using a structure resembling biological neuronal information processing. The filter is fully configurable, from a “transparent mode” to a very restrictive mode. Based on an analysis of configuration parameters, three main configurations are given: weak, medium and restrictive. Using data from a DVS event camera, results for a similarity detection algorithm show that event data can be reduced up to 30% while maintaining the same similarity index when compared to unfiltered data. Data reduction can reach 85% with a penalty of 15% in similarity index compared to the original data. An object tracking algorithm was also used to compare results of the proposed filter with other existing filter. The LDSI filter provides less error (4.86 ± 1.87) when compared to the background activity filter (5.01 ± 1.93). The algorithm was tested under a PC using pre-recorded datasets, and its FPGA implementation was also carried out. A Xilinx Virtex6 FPGA received data from a 128 × 128 DVS camera, applied the LDSI algorithm, created a AER dataflow and sent the data to the PC for data analysis and visualization. The FPGA could run at 177 MHz clock speed with a low resource usage (671 LUT and 40 Block RAM for the whole system), showing real time operation capabilities and very low resource usage. The results show that, using an adequate filter parameter tuning, the relevant information from the scene is kept while fewer events are generated (i.e., fewer generated data).

A high performance hardware architecture for non-negative tensor factorization

Non-negative tensor factorization (NTF) algorithm is an emerging method for high-dimensional data analysis, which is applied in many fields such as computer vision, and bioinformatics. This paper presents an effective method to accelerate NTF computations and proposes a corresponding hardware architecture, which consists of multiple processing units. The decomposed factors are calculated by using shared intermediate results. By using the proposed method, NTF can be implemented in parallel and hardware resources can be saved by sharing. In this paper, we evaluate the proposed architecture on Xilinx Virtex-6 FPGA XC6VLX760T and apply it into 2 applications, i.e. video background estimation and facial images processing. The experimental results show that the proposed hardware architecture achieves over 80 times faster than CPU implementation of NTF. Compared with the implementations on GPGPU, the proposed architecture achieves nearly the same speedup. While the strategy in this paper is applied to GPU platforms, the execution time can be reduced by a half, due to the computational sharing in this paper.

Delta-Sigma Modulation for Next Generation Fronthaul Interface

A new function split option for the next generation fronthaul interface (NGFI) is demonstrated based on all-digital RF transmitter using bandpass delta-sigma modulation. Different from other low layer split (LLS) options, such as option 6 (MAC-PHY), 7 (high-low PHY), and 8 (CPRI), the proposed option 9 implements RF functions in the digital domain, and splits within the RF layer, with high-RF layer centralized in the distributed unit (DU) and low-RF layer distributed in remote radio units (RRUs). A proof-of-concept all-digital RF transmitter based on real-time delta-sigma modulation is implemented using a Xilinx Virtex-7 FPGA. A 5-GSa/s delta-sigma modulator is demonstrated to encode LTE/5G signals with bandwidth up to 252 MHz and modulation format up to 1024-QAM to a 5-Gb/s OOK signal, which is transmitted over 30-km single-mode fiber from DU to RRU. To relax the FPGA speed requirement, a 32-pipeline architecture is designed. Two-carrier aggregation of 5G and 14-carrier aggregation of LTE signals are demonstrated with error vector magnitude (EVM) performance satisfying the 3GPP specifications. Compared with option 8 (CPRI), although the proposed option 9 split occurs at a lower level, it offers improved spectral efficiency and reduced NGFI data rate than CPRI. Moreover, other LLS options, such as 6, 7, and 8, all require a complete RF layer implemented in the analog domain at remote cell sites; whereas option 9 realizes high-RF layer in the digital domain at DU, and eliminates the need of analog RF devices, such as DAC, local oscillator and mixer at RRU, which not only makes low-cost, energy-efficient, and small-footprint cell sites possible for the wide deployment of small cells, but also paves the road toward software defined radio (SDR) and virtualization of DU and RRU for improved compatibility and reconfigurability among multiple radio access technologies (multi-RATs). Given its centralized architecture and deterministic latency, option 9 is suitable for radio coordination applications, and has potential in low-frequency narrowband scenarios with cost, power, and/or size sensitive cell sites, such as massive machine type communication (mMTC) and narrowband internet of things (NB-IoT).

Implementation of fast FFT design for 128-point using Radix-22 CFA

In this paper, implementation of fast FFT design for 128- point using Radix-22 CFA is presented. This research uses a common factor algorithm which is based on Radix-22. A 2-point DFT butterfly structure is the lowest complexity structure and Radix-22 CFA is used to reduce logic and area by reducing the number of twiddle factors. The VHDL code is written and synthesized using Xilinx FPGA device xc7vx330t-3ffg1761 to implement the proposed design. This design is coded in VHDL and MATLAB. VHDL code is targeted to synthesize into Xilinx Virtex-7 FPGA and simulated into ModelSim PE Student Edition 10.4a. MATLAB code is simulated into MATLAB 2012. The proposed design achieves 149.822 MHz clock frequency, used 2802 slices on the Virtex-7 and SQNR 33.49 dB at 16-bit I/O word length.

Flexible elliptic curve cryptography coprocessor using scalable finite field arithmetic blocks on FPGAs

The increasing dependency of modern day information transferred over the network demands an increasing need of efficient implementations of security protocols on server and client devices to process the encryption and decryption of messages. This paper presents the design of an efficient scalable and unified Elliptic Curve Cryptography (ECC) coprocessor that takes advantage of the DSP48E slices on Xilinx FPGAs. The proposed coprocessor is able to evaluate the elliptic curve point multiplication (ECPM) for all 15 curves recommended by the National Institute of Standards and Technology (NIST). The DSP48E slices available in Xilinx FPGAs improve the performance of the coprocessor and provide the ability to evaluate dual-field arithmetic. The coprocessor has been implemented on a Xilinx Virtex-5 FPGA and it requires 4244 registers, 8316 LUTs, 2291 slices, 5 BRAMs and 25 DSP48E slices. It can evaluate the ECPM between 0.857 ms and 9.662 ms for prime curves and between 0.239 ms and 4.523 ms for binary curves. This paper also proposes a set of scalable finite field arithmetic blocks that can be programmed to implement different ECPM algorithms. In comparison with other ECC coprocessors in the current literature, the proposed design is very competitive in terms of timing performance and hardware resource utilization, while combining the scalability and dual-field features that are not available in other designs.