Xilinx Zynq Research Articles

DESIGN AND ANALYSIS OF NOVEL PARALLEL PREFIX ADDERS FOR VLSI CIRCUITS

Arithmetic Logic Unit is the brain of all processors, is composed of an Adder circuit. The main component of multiplier circuits is the adder, which performs subtraction (by 2’s complement arithmetic). Since the most fundamental operation in mathematics is addition, and the adder is the most essential part of the processor, the study of VLSI arithmetic has required many digital VLSI researchers. When designing digital systems employing the VLSI approach, the digital adder plays a major role. Low power VLSI based adder designs perform poorly because of the propagation delay issue. With the aid of the PPA design, an assessment of adders’ availability for low power VLSI designs with minimal propagation delay is conducted. Using these performance measures, this study compares and evaluates the performance of several parallel prefix adders, allowing readers to select the optimum adder architecture for their application Specific Integrated Circuits implementations. The three adder topologies taken into considered in this Article include the Han carlson adder, Brent kung, Kogge stone adders. Xilinx ZYNQ XC7Z020 (7000 series) SoC is used to implement the adders using the Vivado Design Suite 2014 and Verilog.

Flexible Updating of Internet of Things Computing Functions through Optimizing Dynamic Partial Reconfiguration

With applications to become increasingly compute- and data-intensive, requiring more processing power, many Internet of Things (IoT) platforms in robots, drones, and autonomous vehicles that implement neural network inference, cryptographic functions or signal processing (e.g., multimedia, communication), employ field programmable gate arrays (FPGAs). At the same time, dynamic partial reconfiguration (DPR) in modern FPGAs enable changing the function of a part of the FPGA by dynamically loading new bitstreams to the logic regions without affecting the function of other parts of the FPGA. This is especially useful to update functions of IoT devices while in operation for bug fixing or functionality adjustments and, more importantly, when these IoT devices integrate low-cost FPGAs that can hardly realize many hard accelerators. To deal with one of the major limitations of using partial reconfiguration in IoT devices, this work introduces techniques to flexibly use DPR, namely, FLEXDPR, by sharing reconfigurable partitions among different accelerator functions and by supporting virtual relocation of these functions. Experimental results on the Xilinx Zynq-7000 platform reveal energy and latency efficiency improvements of about 20%, on average. Overall, the suggested approach can reduce partial reconfiguration overhead while easing the scheduler’s decisions for the deployment of hardware functions throughout time and space in a performance-conscious manner.

Pflow: An end-to-end heterogeneous acceleration framework for CNN inference on FPGAs

Field-Programmable Gate Arrays (FPGAs), renowned for their high performance per watt, are extensively utilized to accelerate Convolutional Neural Networks (CNNs) in edge computing environments, primarily employing dataflow-based and instruction set-based approaches. Compared to the instruction set-based approach that features fast and versatile circuit design, the dataflow-based approach can significantly enhance performance at the expense of design versatility. Nevertheless, edge computing environments require both high energy efficiency and adaptability to various scenarios. This paper proposes a novel end-to-end heterogeneous acceleration framework for CNN inference on FPGAs, named Pflow. The basic idea is to decouple network deployment and hardware details with a hardware–software co-design approach. First, a dataflow accelerator with an adaptive scheduling strategy is proposed. The adaptive scheduling strategy, along with a scalable design, maximizes hardware utilization in terms of computing resources and bandwidth. Secondly, we design a novel operator-perception method to automate the processes of network reconstruction and operator fusion. Thirdly, we integrate Pflow into the industrial-grade deep learning framework Paddle-Lite. We evaluate Pflow by implementing several networks on two representative FPGA platforms. Experimental results demonstrate that Pflow achieves energy efficiencies of 46.5 GOPS/W on Xilinx Zynq Ultrascale+ MPSoC 3EG and 59.4 GOPS/W on Virtex UltraScale+ XCVU13P. It also reaches a throughput of up to 255.7 GOPS on the former and 3.686 TOPS on the latter.

Hardware Trojan Attacks on the Reconfigurable Interconnections of Field-Programmable Gate Array-Based Convolutional Neural Network Accelerators and a Physically Unclonable Function-Based Countermeasure Detection Technique.

Convolutional neural networks (CNNs) have demonstrated significant superiority in modern artificial intelligence (AI) applications. To accelerate the inference process of CNNs, reconfigurable CNN accelerators that support diverse networks are widely employed for AI systems. Given the ubiquitous deployment of these AI systems, there is a growing concern regarding the security of CNN accelerators and the potential attacks they may face, including hardware Trojans. This paper proposes a hardware Trojan designed to attack a crucial component of FPGA-based CNN accelerators: the reconfigurable interconnection network. Specifically, the hardware Trojan alters the data paths during activation, resulting in incorrect connections in the arithmetic circuit and consequently causing erroneous convolutional computations. To address this issue, the paper introduces a novel detection technique based on physically unclonable functions (PUFs) to safeguard the reconfigurable interconnection network against hardware Trojan attacks. Experimental results demonstrate that by incorporating a mere 0.27% hardware overhead to the accelerator, the proposed hardware Trojan can degrade the inference accuracy of popular neural network architectures, including LeNet, AlexNet, and VGG, by a significant range of 8.93% to 86.20%. The implemented arbiter-PUF circuit on a Xilinx Zynq XC7Z100 platform successfully detects the presence and location of hardware Trojans in a reconfigurable interconnection network. This research highlights the vulnerability of reconfigurable CNN accelerators to hardware Trojan attacks and proposes a promising detection technique to mitigate potential security risks. The findings underscore the importance of addressing hardware security concerns in the design and deployment of AI systems utilizing FPGA-based CNN accelerators.

Implementation of a non-linear SVM classification for seizure EEG signal analysis on FPGA

An automatic detection method for disease diagnosis plays an important role in the medical field. A computer-aided diagnosis (CAD) system for seizure detection using electroencephalogram (EEG) data is significant in protecting patients' lives. This paper presents machine learning algorithm-based seizure detection approach implemented in both software and hardware using EEG recordings. The input EEG signal is subjected to pre-processing, decomposition using wavelet transform and classification by a support vector machine (SVM) classifier. The maximum and variance statistical values of the decomposed EEG sub-bands are computed to generate a feature vector, while classification accuracy and computational complexity are taken into account. Gaussian Radial Basis Function (RBF) kernel based Non-Linear SVM (NLSVM) is used in this proposed approach to solve both two-class and three-class classification problems. In three-class classification, the one-against-one (OAO) technique is used. The competency of the proposed technique is evaluated using two distinct datasets provided by Bonn University, Germany & Neurology and Sleep Centre, New Delhi. The adequate parameters of the NLSVM classifier model are determined by using MATLAB software in the training phase and the best performing NLSVM model is selected for implementation on the Field-Programmable Gate Array (FPGA). The proposed seizure detection method is implemented with Verilog code and examined on a Xilinx Zynq-7000 XC7Z020 FPGA board to evaluate its performance. The experimental results show that the proposed method with a minimal number of features achieved a good performance metric for seizure detection and is comparable with that of the state-of-the-art methods.

An FPGA implementation of Bayesian inference with spiking neural networks.

Spiking neural networks (SNNs), as brain-inspired neural network models based on spikes, have the advantage of processing information with low complexity and efficient energy consumption. Currently, there is a growing trend to design hardware accelerators for dedicated SNNs to overcome the limitation of running under the traditional von Neumann architecture. Probabilistic sampling is an effective modeling approach for implementing SNNs to simulate the brain to achieve Bayesian inference. However, sampling consumes considerable time. It is highly demanding for specific hardware implementation of SNN sampling models to accelerate inference operations. Hereby, we design a hardware accelerator based on FPGA to speed up the execution of SNN algorithms by parallelization. We use streaming pipelining and array partitioning operations to achieve model operation acceleration with the least possible resource consumption, and combine the Python productivity for Zynq (PYNQ) framework to implement the model migration to the FPGA while increasing the speed of model operations. We verify the functionality and performance of the hardware architecture on the Xilinx Zynq ZCU104. The experimental results show that the hardware accelerator of the SNN sampling model proposed can significantly improve the computing speed while ensuring the accuracy of inference. In addition, Bayesian inference for spiking neural networks through the PYNQ framework can fully optimize the high performance and low power consumption of FPGAs in embedded applications. Taken together, our proposed FPGA implementation of Bayesian inference with SNNs has great potential for a wide range of applications, it can be ideal for implementing complex probabilistic model inference in embedded systems.

Artificial Intelligence-Based Field-Programmable Gate Array Accelerator for Electric Vehicles Battery Management System

<div>The swift progress of electric vehicles (EVs) and hybrid electric vehicles (HEVs) has driven advancements in battery management systems (BMS). However, optimizing the algorithms that drive these systems remains a challenge. Recent breakthroughs in data science, particularly in deep learning networks, have introduced the long–short-term memory (LSTM) network as a solution for sequence problems. While graphics processing units (GPUs) and application-specific integrated circuits (ASICs) have been used to improve performance in AI-based applications, field-programmable gate arrays (FPGAs) have gained popularity due to their low power consumption and high-speed acceleration, making them ideal for artificial intelligence (AI) implementation. One of the critical components of EVs and HEVs is the BMS, which performs operations to optimize the use of energy stored in lithium-ion batteries (LiBs). Due to the nonlinear electrochemical nature of these batteries, estimating states of charge (SoC), states of health (SoH), and remaining useful life (RUL) is challenging. This article proposes an advanced AI-based BMS that uses LSTM to accurately estimate LiB states, providing crucial information for battery performance optimization. The proposed design is implemented in Python for training and validation. The hardware prototype is synthesized using Xilinx Vitis High-Level Synthesis (HLS) and implemented on Xilinx Zynq System-on-Chip (SoC) PYNQ Z2 board, achieving low root mean squared error (RMSE) values of 0.3438 and 0.3681 in training and validation, respectively.</div>

Design of a High Speed 360-degree Panoramic Video Acquisition System Based on FPGA and USB 3.0

This paper presents a FPGA-based hardware architecture for capturing real-time panoramic images and the parallel implementation of an image stitching algorithm based on the scale-invariant feature transform (SIFT) features. First, the system transfers the images captured by five CMOS sensors to the designed FPGA board through the FMC adapter plate. Then, the system employs the FPGA-based parallel computing to extract the SIFT features and detect the best matching region and points for image registration. Finally, in order to obtain the panoramic image with smooth changes at the junctions, images of the adjacent images are fused. Using the designed FPGA platform makes it possible to extract the SIFT and stitch the images in real-time, which is not realized in most panoramic imaging systems. The panoramic system, developed using the Xilinx Zynq®-7000 all programmable SOC, can capture video of 5*640*480 images at the speed of 60 fps. To enable high-speed image transfer from the imaging system to the host computer, the USB3.0 interface with the transmission speed of 359MB/s has been developed. The real-time efficiency of the parallel system will be demonstrated by the simulations and experiments.

Supervised Contrastive Learning Framework and Hardware Implementation of Learned ResNet for Real-time Respiratory Sound Classification.

This paper presents a supervised contrastive learning (SCL) framework for respiratory sound classification and the hardware implementation of learned ResNet on field programmable gate array (FPGA) for real-time monitoring. At the algorithmic level, multiple techniques such as features augmentation and MixUp are combined holistically to mitigate the impact of data scarcity and imbalanced classes in the training dataset. Bayesian optimization further enhances the classification accuracy through parameter tuning in pre-processing and SCL. The proposed framework achieves 0.8725 total score (including runtime score) on a ResNet-18 model in both event and record multi-class classification tasks using the SJTU Paediatric Respiratory Sound Database (SPRSound). In addition, algorithm-hardware co-optimizations including Quantization-Aware Training (QAT), merge of network layers, optimization of memory size and number of parallel threads are performed for hardware implementation on FPGA. This approach reduces 40% model size and 70% computation latency. The learned ResNet is implemented on a Xilinx Zynq ZCU102 FPGA with 16ms latency and less than 2% inference score degradation compared to the software model.

Research on Convolutional Neural Network Inference Acceleration and Performance Optimization for Edge Intelligence.

In recent years, edge intelligence (EI) has emerged, combining edge computing with AI, and specifically deep learning, to run AI algorithms directly on edge devices. In practical applications, EI faces challenges related to computational power, power consumption, size, and cost, with the primary challenge being the trade-off between computational power and power consumption. This has rendered traditional computing platforms unsustainable, making heterogeneous parallel computing platforms a crucial pathway for implementing EI. In our research, we leveraged the Xilinx Zynq 7000 heterogeneous computing platform, employed high-level synthesis (HLS) for design, and implemented two different accelerators for LeNet-5 using loop unrolling and pipelining optimization techniques. The experimental results show that when running at a clock speed of 100 MHz, the PIPELINE accelerator, compared to the UNROLL accelerator, experiences an 8.09% increase in power consumption but speeds up by 14.972 times, making the PIPELINE accelerator superior in performance. Compared to the CPU, the PIPELINE accelerator reduces power consumption by 91.37% and speeds up by 70.387 times, while compared to the GPU, it reduces power consumption by 93.35%. This study provides two different optimization schemes for edge intelligence applications through design and experimentation and demonstrates the impact of different quantization methods on FPGA resource consumption. These experimental results can provide a reference for practical applications, thereby providing a reference hardware acceleration scheme for edge intelligence applications.

Synchronisation of linear accelerator for fruit irradiation with FPGA-based system

Linear accelerator (LINAC) has been broadly used in various applications in recent years. For instance, the LINAC can produce X-rays and high-energy electrons, which are utilised in radiation therapy for medical purposes and also applied to fruit steriliser for exportation. At present, the prototype of the 6 MeV LINAC for fruit irradiation by using a magnetron radio frequency (RF) source has been developed at Synchrotron Light Research Institute (SLRI) in Nakhon Ratchasima, Thailand. The LINAC consists of several key sub-systems such as pulsed modulators both for electron gun and magnetron used to power the LINAC, magnetic guidance and beam diagnostic systems. All these have been integrated and worked in proper function to reach a proper and stable RF acceleration. Therefore, a timing system is required with well synchronisation for precise transfer of the clock and reference trigs to each sub-system. Furthermore, the low-cost in-house synchronous equipment has been built here for domestic researchers when they would like to apply this system to their work in the future; consequently, the FPGA-based system for real-time synchronisation has been created to achieve the sequences of the LINAC timing system. In this design, the Zybo Z7 development board from the Xilinx Zynq-7000 family is chosen, which integrates the programmable logic (PL) and processing system (PS) in the same chip. The experimental results are presented by the LINAC operation with synchronisation between a precise time and various delay times on both pulsed modulators, which the synchronous technique with accurate time demonstrates excellent performances leading to stable X-ray radiation for fruit irradiation with synchronous operation between the electron gun and magnetron.

Design and development of MTCA.4-based generic control and data acquisition module for CSNS-II and SAPS-TP

A new generation of domestically generic control and data acquisition AMC module has been developed to meet the requirements of the upgrade and renovation of the RCS LLRF system in the CSNS-II project, as well as the horizontal testing needs of the SAPS-TP. This module complies with the MicroTCA.4 standard and utilizes the Xilinx ZYNQ 7045 SOC as the core data processing chip. It can simultaneously run FPGA algorithms and the EPICS IOC remote control application program, serving as an autonomous control node. The module is equipped with 8 channels of 125 MSPS 16-bit ADC and 2 channels of 16-bit DAC with a maximum sampling rate of up to 500 MSPS. It also features standard expansion interface, front optical panel fiber interface, external clock interface, front panel digital IO interface, and more, catering to the needs of multiple systems in accelerator facilities such as radio-frequency, beam diagnostics, and control system. Additionally, the module can function independently for smaller-scale experimental and testing systems, such as the LLRF system for horizontal testing of SAPS-TP. To guarantee the seamless integration and proper operation of the AMC module within the MicroTCA.4 ecosystem, the MMC mezzanine card has been developed and thoroughly tested. In order to further reduce costs for small-scale systems, we optimized the software of the MMC so that the AMC board can run without the MCH module and realize self-health monitoring. For common applications, we have developed a complete software architecture and demo programs, including FPGA firmware, embedded Linux operating system, kernel driver modules, and EPICS IOC demo application programs. Detailed measurements have been conducted on hardware performance such as SNR, SFDR, channel isolation, as well as software performance including AXI DMA data bandwidth and system resources utilization, etc. The measurement results indicate that the module's performance indicators meet the design requirements.

A Novel Implementation Methodology for Error Correction Codes on a Neuromorphic Architecture

The Internet of Things infrastructure connects a massive number of edge devices with an increasing demand for intelligent sensing and inferencing capability. Such data-sensitive functions necessitate energy-efficient and programmable implementations of Error Correction Codes (ECC) and decoders. The algorithmic flow of ECCs with concurrent accumulation and comparison types of operations are innately exploitable by neuromorphic architectures for energy efficient execution–an area that is relatively unexplored outside of machine learning applications. For the first time, we propose a methodology to map the hard-decision class of decoder algorithms on a neuromorphic architecture. We present the implementation of the Gallager B (GaB) decoding algorithm on a TrueNorth-inspired architecture that is emulated on the Xilinx Zynq ZCU102 MPSoC. Over this reference implementation, we propose architectural modifications at the neuron block level that result in a reduction of energy consumption by 31% with a negligible increase in resource usage while achieving the same error correction performance.

Application Specific Reconfigurable Processor for Eyeblink Detection from Dual-Channel EOG Signal

The electrooculogram (EOG) is one of the most significant signals carrying eye movement information, such as blinks and saccades. There are many human–computer interface (HCI) applications based on eye blinks. For example, the detection of eye blinks can be useful for paralyzed people in controlling wheelchairs. Eye blink features from EOG signals can be useful in drowsiness detection. In some applications of electroencephalograms (EEGs), eye blinks are considered noise. The accurate detection of eye blinks can help achieve denoised EEG signals. In this paper, we aimed to design an application-specific reconfigurable binary EOG signal processor to classify blinks and saccades. This work used dual-channel EOG signals containing horizontal and vertical EOG signals. At first, the EOG signals were preprocessed, and then, by extracting only two features, the root mean square (RMS) and standard deviation (STD), blink and saccades were classified. In the classification stage, 97.5% accuracy was obtained using a support vector machine (SVM) at the simulation level. Further, we implemented the system on Xilinx Zynq-7000 FPGAs by hardware/software co-design. The processing was entirely carried out using a hybrid serial–parallel technique for low-power hardware optimization. The overall hardware accuracy for detecting blinks was 95%. The on-chip power consumption for this design was 0.8 watts, whereas the dynamic power was 0.684 watts (86%), and the static power was 0.116 watts (14%).

Digital circuit for switch contact bounce analysis

This article discusses the issue of studying the parameters of the bounce of electrical contacts of switches in digital systems. Digital circuits of bounce analyzer are described. The results of experimental studies of the behavior of electrical contacts of various buttons and switches are presented. It is shown that various electric switches have random and unique characteristics, which can be used to solve the problems of random numbers generating, identifying of digital devices and user’s authentication. Prototyping of the proposed circuits was carried out on Digilent ZYBO Z7-10 debug boards, digital circuits were designed in VHDL for the Xilinx Zynq-7000 FPGA chip.

An AER-based spiking convolution neural network system for image classification with low latency and high energy efficiency

Spiking neural network is used to solve the problems of power consumption and computation requirement of the traditional artificial neural network. This paper proposes an event-driven multilayer spiking convolutional neural network (SCNN) hardware system for the image classification task. The proposed hardware system consists of a microcontroller unit (MCU) and an SCNN processor. Input images are temporally encoded to spike trains in the form of address event representation (AER) by MCU, and sent to the SCNN processor to execute AER-based spike-centric convolution in order to reduce redundant operations and get the classification result efficiently. By rearranging the storage structure of weights of synapses and membrane potential (MP) of spiking neurons, multi-channel parallel MP updating is realized to reduce latency. In addition, FIFOs are inserted between the spiking layers to construct a pipeline structure. The hardware architecture of the proposed system is implemented on the Xilinx ZYNQ-7000 platform. At the operating frequency of 100 MHz, the proposed SCNN processor has a speed of 400classifications/s and 80uJ/inference.

Radiation-Induced Noise Resilience of Neuromorphic Architectures

Neuromorphic event-based networks use asynchronous time-dependent information to extract features from input data that can allow for edge-based distributed applications such as object recognition. The noise resilience properties of such networks, especially in the context of space applications, are yet to be explored. In this paper, we use the hierarchy of time surfaces (HOTS) algorithm, which is one of the neuromorphic algorithms, to understand the least and most resilient modules in a neuromorphic network. The HOTS algorithm relies on the computing of time surfaces that maps the temporal delays between neighboring pixels into normalized features that involve many computations that are also found in other neuromorphic networks such as exponential decays, distance computations, etcetera. We implemented HOTS on a Digilent PYNQ board with a Xilinx Zynq 7020 system on a chip, and we subjected the boards running the HOTS network inference to neutron radiation at the Los Alamos Neutron Science Center. Furthermore, we used simulation models from our previous similar experiments on the event-based sensor to create a neutron induced noise model to quantify the effect of this noise on the overall performance of the network. This experiment provides the preliminary measurements of the reliability of the HOTS algorithm and proposes methods to create a more reliable HOTS architecture in future spacecraft missions.

Convolutional Tsetlin Machine-based Training and Inference Accelerator for 2-D Pattern Classification

The Tsetlin Machine (TM) is a machine learning algorithm based on an ensemble of Tsetlin Automata (TAs) that learns propositional logic expressions from Boolean input features. In this paper, the design and implementation of a Field Programmable Gate Array (FPGA) accelerator based on the Convolutional Tsetlin Machine (CTM) is presented. The accelerator performs classification of two pattern classes in 4 × 4 Boolean images with a 2 × 2 convolution window. Specifically, there are two separate TMs, one per class. Each TM comprises 40 propositional logic formulas, denoted as clauses, which are conjunctions of literals. Include/exclude actions from the TAs determine which literals are included in each clause. The accelerator supports full training, including random patch selection during convolution based on parallel reservoir sampling across all clauses. The design is implemented on a Xilinx Zynq XC7Z020 FPGA platform. With an operating clock speed of 40 MHz, the accelerator achieves a classification rate of 4.4 million images per second with an energy per classification of 0.6 μJ. The mean test accuracy is 99.9% when trained on the 2-dimensional Noisy XOR dataset with 40% noise in the training labels. To achieve this performance, which is on par with the original software implementation, Linear Feedback Shift Register (LFSR) random number generators of minimum 16 bits are required. The solution demonstrates the core principles of a CTM and can be scaled to operate on multi-class systems for larger images.

Lightweight Cryptography for Connected Vehicles Communication Security on Edge Devices

Recent advances in mobile connection technology have been involved in every aspect of modern life. Even vehicles are becoming more connected, with the ability to communicate without human intervention. The main idea of connected vehicles is to exchange information to avoid a potential collision or to warn the driver about stop signs/lights. To achieve a wide range of connections between vehicles, they must be equipped with connected devices such as Bluetooth, wi-fi, and cellular connectivity. However, communication raises security issues with regard to cybersecurity attacks that attempt to collect confidential information or to take control of the vehicle by forcing unintended braking or steering. In this paper, we proposed a secure vehicle-to-vehicle (V2V) communication approach by deploying a secure communication protocol based on a key management process and a cryptography system to encrypt exchanged data. The proposed key management process was designed to resist many attacks and eliminate connections to the infrastructure for key generation. Since vehicles are equipped with embedded devices with limited computation resources, a lightweight cryptography algorithm was used. The light encryption device (LED) block cipher was used to encrypt exchanged data. The LED has a low implementation area on hardware and low power consumption. It is considered to be a perfect solution for security issues in connected vehicles. The proposed data encryption algorithm was synthesized with VHDL on the Xilinx Zynq-7020 FPGA using the Vivado HLS tool. The encryption algorithm was implemented only on the logic of the device. The achieved results proved that the proposed algorithm is suitable for implementation in vehicles due to its low implementation requirements and low power consumption in addition to its high security level against cyber-attacks.

FPGA-Based Feature Extraction and Tracking Accelerator for Real-Time Visual SLAM.

Due to its advantages of low latency, low power consumption, and high flexibility, FPGA-based acceleration technology has been more and more widely studied and applied in the field of computer vision in recent years. An FPGA-based feature extraction and tracking accelerator for real-time visual odometry (VO) and visual simultaneous localization and mapping (V-SLAM) is proposed, which can realize the complete acceleration processing capability of the image front-end. For the first time, we implement a hardware solution that combines features from accelerated segment test (FAST) feature points with Gunnar Farneback (GF) dense optical flow to achieve better feature tracking performance and provide more flexible technical route selection. In order to solve the scale invariance and rotation invariance lacking problems of FAST features, an efficient pyramid module with a five-layer thumbnail structure was designed and implemented. The accelerator was implemented on a modern Xilinx Zynq FPGA. The evaluation results showed that the accelerator could achieve stable tracking of features of violently shaking images and were consistent with the results from MATLAB code running on PCs. Compared to PC CPUs, which require seconds of processing time, the processing latency was greatly reduced to the order of milliseconds, making GF dense optical flow an efficient and practical technical solution on the edge side.