Xilinx Environment Research Articles

Light-Weight Present Block Cipher Model for IoT Security on FPGA

The Internet of Things (IoT) plays an essential role in connecting a small number of billion devices with people for diverse applications. The security and privacy with authentication are challenging work for IoT devices. A light-weight block cipher is designed and modeled with IoT security for real-time scenarios to overcome the above challenges. The light-weight PRESENT module with the integration of encryption (E)-decryption (D) is modeled and implemented on FPGA. The PRESENT module has 64-bit data input with 80/128/256-bit symmetric keys for IoT security. The PRESENT module performs16/32/64 round operations for state register and key updation. The design mainly uses Substitution-permutation (SP) network for state updation. The permutation layer is used to create more diffusion and confusion in the state for unauthorized access. The results and analysis of the PRESENT-80/128/256 are designed using Verilog-HDL with Xilinx Environment and implemented on Artix-7 FPGA. The PRESENT-80/128/256 module is compared with similar recent works with performance improvements. Similarly, the proposed work is compared with different light-weight algorithms with improvements for better security in IoT devices. The proposed PRESENT-256 module with 64-rounds on Artix-7 FPGA utilizes less than 2% Chip area (Slices and LUTs), works at 412.4 MHz frequency, and consumes 192 mW total power and 0.58 Mbps/slice of hardware efficiency.

Design and Implementation of 802.15.4 Transceiver for Wireless Personal Area Networks (WPANs) on FPGA

The IEEE 802.15.4 standard provides mainly accessing, monitoring, and controlling capability of the Wireless devices. This standard supports short-range wireless communications and Low Rate (LR) - Wireless Personal Area Networks (WPANs). This manuscript presents the fully integrated digital 802.15.4 Transceiver, which suitable to ZigBee Device Standard at 2.4GHz range. The 802.15.4 Transceiver design includes an 8-bit input data sequence mapped to lower and Upper Symbols followed by Chip-sequence conversion as per the IEEE standard. The chip sequences are mapped separately as even and odd sequences used for the Offset-QPSK Modulation. The chip synchronization achieved by using a proper clocking mechanism on the receiver side. The 802.15.4 Transceiver design is implemented on Artix-7 FPGA using Xilinx Environment. The hardware constraints like Area (Slices), Frequency, and Power are analyzed. The proposed work also compared with existing similar approaches with more significant improvements in chip area and Power.

Implementation of multi-operand addition in FPGA using high-level synthesis

The paper presents the results of high-level synthesis (HLS) of multi-operand adders in FPGA using the Vivado Xilinx environment. The aim was to estimate the hardware amount and latency of adders described in C-code. The main task of the presented experiments was to compare the implementations of the carry-save adder (CSA) type multi-operand adders obtained as the effect of the HLS synthesis and those based on the basic component being 4-operand adder with fast carry-chain available in FPGA’s implemented in Verilog. However, the HLS synthesis simplifies the design and prototyping process but the received results indicate that the circuit obtained as the result of such synthesis requires twice more resources and is slower than its counterpart design using Verilog.

A Novel Less Area Computation Sharing High Speed Multiplier Architecture for FIR Filter Design

High performance multiplier designs are the prime need of emerging digital filtering operations. This research study presents a novel architecture of reduced area computation sharing multiplier for Finite Impulse Response (FIR) filter. The same architecture is extended for the floating point applications. The chosen pre-computer alphabet set is the most prominent feature of this architecture. The proposed integer based Computation Sharing High speed Multiplier (CSHM) efficiently computes the vector scalar product based on the distributed arithmetic. The proposed CSHM (8*8) shows 29.81% of area and 46% of power optimization over existing CSHM style. The experimental results for Look up Table (LUT) based implementation shows 57% improvement than the LUT required to implement a existing 8*8 CSHM based FIR filter. The proposed design style is also extended for Floating Point (FP) multiplication. The 4 tap Floating Point Finite Impulse Response (FP FIR) filter is designed in Xilinx environment (No. of LUT's 5919) and TSMC 180 nm technology (power 29.5 mW and area 212636.79 um^2) using proposed CSHM. The performance results get improves in terms of power and area over conventional design style.

FPGA Based Embedded Multiprocessor Architecture

Multiprocessor is a typical subject within the Computer architecture field of scope. A new methodology based on practical sessions with real devices and design is proposed. Embedded multiprocessor design presents challenges and opportunities that stem from task coarse granularity and the large number of inputs and outputs for each task. We have therefore designed a new architecture called embedded concurrent computing (ECC), which is implementing on FPGA chip using VHDL. The design methodology is expected to allow scalable embedded multiprocessors for system expansion. In recent decades, two forces have driven the increase of the processor performance: Advances in very large-scale integration (VLSI) technology and Micro architectural enhancements. Therefore, we aim to design the full architecture of an embedded processor for realistic to perform arithmetic, logical, shifting and branching operations. We will be synthesize and evaluated the embedded system based on Xilinx environment. Processor performance is going to be improving through clock speed increases and the clock speed increases and the exploitation of instruction- level parallelism. We will be designing embedded multiprocessor based on Xilinx environment or Modelsim environment.

IMPLEMENTATION OF USB TRANSCEIVER MACROCELL INTERFACE

The universal serial bus (USB) transceiver macro cell interface (UTMI) is a two wire, bi-directional serial bus interface. UTMI consists of transmitting and receiving sections, in which the transmitter of the UTMI sends data to different USB devices through D+ and Dlines whereas the receiver gets data on the same lines. UTMI is one of the important functional blocks of USB controller, which can transmit and receive data to or from USB devices. There are three functional blocks present in USB controller; those are Serial Interface Engine (SIE), UTMI and Device Specific Logic (DSL). The parallel data from SIE is taken into the transmit hold register and this data is sent to transmit shift register from where the data is converted serially. This serial data is bit stuffed to perform data transitions for clock recovery and NRZI (1) encoding. Then the encoded data is sent on to the serial bus. When the data is received on the serial bus, it is decoded, bit unstuffed and is sent to receive shift register. After the shift register is full, the Data is sent to receive hold register. This presentation reveals the FPGA implementation of UTMI transmission rate providing with USB 2.0 specifications. Further UTMI has been designed by using VHDL code and simulated, synthesized and programmed to the targeted Spartan family of FPGA in the Xilinx environment.

Proposed hardware architectures of particle filter for object tracking

In this article, efficient hardware architectures for particle filter (PF) are presented. We propose three different architectures for Sequential Importance Resampling Filter (SIRF) implementation. The first architecture is a two-step sequential PF machine, where particle sampling, weight, and output calculations are carried out in parallel during the first step followed by sequential resampling in the second step. For the weight computation step, a piecewise linear function is used instead of the classical exponential function. This decreases the complexity of the architecture without degrading the results. The second architecture speeds up the resampling step via a parallel, rather than a serial, architecture. This second architecture targets a balance between hardware resources and the speed of operation. The third architecture implements the SIRF as a distributed PF composed of several processing elements and central unit. All the proposed architectures are captured using VHDL synthesized using Xilinx environment, and verified using the ModelSim simulator. Synthesis results confirmed the resource reduction and speed up advantages of our architectures.