Xilinx ISE Design Suite Research Articles

GMC-crypto: Low latency implementation of ECC point multiplication for generic Montgomery curves over GF(p)

Elliptic Curve Cryptography (ECC) is the front-runner among available public key cryptography (PKC) schemes due to its potential to offer higher security per key bit. All ECC-based cryptosystems heavily rely on point multiplication operation where its efficient realization has attained notable focus in the research community. Low latency implementation of the point multiplication operation is frequently required in high-speed applications such as online authentication and web server certification. This paper presents a low latency ECC point multiplication architecture for Montgomery curves over generic prime filed GF(p). The proposed architecture is able to operate for a general prime modulus without any constraints on its structure. It is based on a new novel pipelined modular multiplier developed using the Montgomery multiplication and the Karatsuba-Offman technique with a four-part splitting methodology. The Montgomery ladder approach is adopted on a system level, where a high-speed scheduling strategy to efficiently execute GF(p) operations is also presented. Due to these circuit and system-level optimizations, the proposed design delivers low-latency results without a significant increase in resource consumption. The proposed architecture is described in Verilog-HDL for 256-bit key lengths and implemented on Virtex-7 and Virtex-6 FPGA platforms using Xilinx ISE Design Suite. On the Virtex-7 FPGA platform, it performs a 256-bit point multiplication operation in just 110.9 us with a throughput of almost 9017 operations per second. The implementation results demonstrate that despite its generic nature, it produces low latency as compared to the state-of-the-art. Therefore, it has prominent prospects to be used in high-speed authentication and certification applications.

ASIC Design and Implementation of Automated Coffee and Tea Brewing System with FPGA Validation

Abstract: This paper presents a pioneering approach to enhance the efficiency of automated coffee and tea brewing systems through the integration of an ASIC-GDSII and FPGA validation. Leveraging the power of 45nm CMOS Technology, the design achieves substantial reductions in area, power consumption, and delay. The Verilog HDL code undergoes meticulous verification using Cadence tools like Genus and Innovus, ensuring optimal design performance. Innovus validates timing constraints, ensuring adherence to acceptable delay parameters. The resulting compact design not only minimizes power consumption but also effectively addresses leakage issues. These comprehensive optimizations meet stringent performance, area, and power requirements, elevating the operational efficiency of automated brewing systems. Furthermore, the control algorithm is synthesized and implemented using Xilinx's ISE Design Suite, followed by validation on SPARTAN 6 FPGA, providing invaluable insights for future synthesis and implementation endeavors.

Design analysis of moth-flame optimized fault tolerant technique for minimally buffered network-on-chip router

<span>A network on a chip is a solitary silicon chip utilized to perform the communication characteristics of large-scale (LSI) to very large-scale integration (VLSI) systems. Network-on-chip (NoC) architecture includes links, network interfaces (NI), and routers to unite with external memories or processors. NoC is designed to flow messages from the source module to the destination module through several links involving routing decisions. <br /> The design of NoC is complex and the buffer section’s expensiveness creates problems while providing secured data service. Moreover, routers and links in NoC setups are liable to faults. This work introduces a minimal buffered router, and the faults in the network are optimized using moth flame optimized (MFO) fault-tolerant technique. The software named Xilinx ISE design suite 14.5 is employed for the minimum buffered router model. <br /> The suggested scheme is operated with less area, low power (0.241 mW), and high speed (965.261 Megahertz (MHz)) when matched with previous works.</span>

Implementation of Ripple Carry Adder Design for Optimal VLSI Performance

In the province of wireless receivers, biomedical equipment, and portable/mobile devices, the demand for Very Large Scale Integration (VLSI) systems that optimize space, minimize power consumption, and deliver high performance is dominant. At the core of these systems, adders play a pivotal role as the primary component of arithmetic units. This paper proposes a ripple carry propagate adder with a high-speed area-efficient. The two’s complement representation is employed for adding two numbers, a common practice in various systems dealing with n-bit input sequences. Microprocessors and digital signal processing use these carry adders. The carry output of every finished adder stage is useful as a carry input to the one behind it. This procedure is continued until the last complete adder stage is reached. Each carry output bit in an entire adder is therefore rippled to the next stage. An exact (forward) carry adder be linked with the proposed structure to generate hybrid adders with tunable accuracy levels. The practical implementation of proposed model is carried out using Xilinx ISE Design Suite 13.4, showcasing its feasibility for real-world applications.

Area‐time efficient point multiplication architecture on twisted Edwards curve over general prime field GF(p)

AbstractElliptic curve point multiplication is the main primitive required in almost all security schemes using elliptic curve cryptography (ECC). It is the leading computationally intensive operation that sets the overall performance of the associated cryptosystem. This work presents a highly novel area–time efficient elliptic curve point multiplier over a general prime field . It is based on an efficient radix‐23 parallel multiplier, which performs a ‐bit multiplication in clock cycles. On the system level, the twisted Edwards curves with unified point addition using projective coordinates are adopted, where an efficient scheduling technique is presented to schedule several operations on deployed modular arithmetic units. Due to the introduced optimization at different stages of the design, latency, hardware resource requirement, and total clock cycle count are reduced significantly. Synthesis, and implementation of the proposed design over different Xilinx FPGA platforms are completed using the Xilinx ISE Design Suite tool for key sizes of 192, 224, and 256 bits. The 256‐bit Xilinx Virtex‐7 FPGA implementation reveals that it completes a single point multiplication operation in 0.8 ms and occupies 6.7K FPGA slices in a clock cycle count of 132.2K. It produces significantly better area–time product and throughput per slice than the contemporary designs. The proposed design also has the potential to counter simple power analysis and timing attacks. Thus, it is an elegant solution to develop ECC‐based cryptosystems for applications, where both speed and hardware resource consumption are important.

An Efficient Crypto Processor Architecture for Side-Channel Resistant Binary Huff Curves on FPGA

This article presents an efficient crypto processor architecture for point multiplication acceleration of side-channel secured Binary Huff Curves (BHC) on FPGA (field-programmable gate array) over GF(2233). We have implemented six finite field polynomial multiplication architectures, i.e., (1) schoolbook, (2) hybrid Karatsuba, (3) 2-way-karatsuba, (4) 3-way-toom-cook, (5) 4-way-toom-cook and (6) digit-parallel-least-significant. For performance evaluation, each implemented polynomial multiplier is integrated with the proposed BHC architecture. Verilog HDL is used for the implementation of all the polynomial multipliers. Moreover, the Xilinx ISE design suite tool is employed as an underlying simulation platform. The implementation results are presented on Xilinx Virtex-6 FPGA devices. The achieved results show that the integration of a hybrid Karatsuba multiplier with the proposed BHC architecture results in lower hardware resources. Similarly, the use of a least-significant-digit-parallel multiplier in the proposed design results in high-speed (in terms of both clock frequency and latency). Consequently, the proposed BHC architecture, integrated with a least-significant-digit-parallel multiplier, is 1.42 times faster and utilizes 1.80 times lower FPGA slices when compared to the most recent BHC accelerator architectures.

Implementation of Dynamic and Efficient Virtual Channel Router for Network on Chip with Virtual Channel Arbitration Reduction and Parallel Switch Allocation Unit

— Network on chip (NoC) is a new method of interconnecting modules in system on chip (SoC). Now a day, it is believed that this new communication subsystem will replace the bus-based architecture and will become dominant in SoC design technology. The performance of NoC mainly depends on the router so it is considered as the crucial part in the NoC design. This paper describes the different factors which affect the NoC performance and provides solution to solve these problems. The proposed router has three architectural modifications which makes it dynamic and efficient as compare to generic virtual channel router. This paper introduced the dynamic buffer allocation scheme in which virtual channels and buffer slots are selected and allocated dynamically depending on the network traffic conditions in real time which in turn increases the throughput. In this paper, we have focused on optimizing the virtual channel arbitration (VA) unit design and switch allocation (SA) unit design as well as focusing the maximum utilization of buffer so that it will result in minimizing the latency, area and power. The source code of the router is written in VHDL hardware description language and the simulation and synthesizing the router is done in Xilinx ISE Design Suite 13.1. The parameters like area, frequency, delay, power, latency and throughput are calculated. The results of this modified virtual channel router are compared with the generic virtual channel router. Keywords—Intellectual Property (IP), Network on Chip (NoC), Network Interface (NI), Switch allocation (SA), System-on-Chip (SoC), Virtual channel (VC), Virtual channel arbitration (VA)

High‐speed parallel reconfigurable Fp multipliers for elliptic curve cryptography applications

AbstractElliptic curve cryptography (ECC) protocols due to higher security strength per bit have been widely accepted and deployed. Finite field multiplication is the most computational intensive operation in data security protocols developed using ECC. This paper presents two high‐speed parallel re‐configurable finite field multipliers: PIMD‐2 and PIMD‐3 over prime field (Fp) for ECC applications. The proposed designs are based on the new novel optimized interleaved multiplication algorithms. This work first identifies room of parallelism by investigating independent operations in the standard interleaved multiplication method and subsequently proposes high‐speed hardware architectures that allow the parallel execution of these operations. Due to the introduced modifications, the critical path delays and clock cycle consumption in the PIMD‐2 and PIMD‐3 designs are reduced simultaneously. The proposed Fp multipliers are synthesized using Xilinx ISE Design Suite and implemented on Virtex‐5 and Virtex‐6 field programmable gate array (FPGA) platforms for common ECC key sizes 160–521 bits. The implementation results reveal that the proposed designs are highly efficient, provided up to 3× improvement in latency with lower area‐delay product and higher throughput per FPGA slice as compared to the state‐of‐the‐art.

Neural net implementation of steam properties on FPGA

Real time applications like model predictive control, monitoring and data reconciliation of power plants and industrial processes employ nonlinear mathematical models and require thermodynamic properties and their derivatives of working fluids. Applications like super heater temperature control based on energy balance and real time data reconciliation, require an efficient and a compact method for simultaneous estimation of thermodynamic properties, and their partial derivatives suitable for implementation in field-programmable gate array (FPGA). However, the complex mathematical formulations of these properties prohibit direct implementations in FPGAs. Single artificial neural network (ANN) architecture is used to replace the entire code in higher level languages, running into a few thousand lines. FPGA implementation of a compact neural network for the entire range of thermodynamic properties is presented. Large arguments in sigmoid function are factored into a product of integer and a fractional part which is represented using series approximation with five terms only and the integers are represented in look up table (LUT). This ensures optimum storage and computational burden for the above applications. The ANN is implemented in IEEE 754 floating point with synthesis in Xilinx ISE design suite using Verilog HDL. The results are presented for a typical pressure versus saturation temperature.

Correction to: An Efficient VLSI Architecture for Fast Motion Estimation Exploiting Zero Motion Prejudgment Technique and a New Quadrant-Based Search Algorithm in HEVC

In this manuscript, new quadrant-based search algorithm with zero motion prejudgment is proposed for motion estimation (ME) in HEVC (High Efficiency Video Coding) standard. The HEVC standard is used to obtain efficient output with low motion estimation time. The proposed quadrant-based search algorithm is a fast block matching algorithm that obtain better block matching amid the current block and reference block. The zero motion prejudgment (ZMP) method is used to find the block, whether it is motion or static and it is used for decreasing the computational complexity (CC) in the proposed quadrant-based search algorithm. The proposed quadrant-based search algorithm with ZMP technique for motion estimation in HEVC is implemented on the FPGA hardware platform. The entire architecture is executed in Verilog HDL with Virtex-5 technology and integrated with Xilinx ISE Design Suite 14.5. The results are integrated into the CIF (352 × 288 pixels) and HD (1280 × 720 pixels) video input sequence. The evaluation metrics like PSNR, Motion estimation time, sum of absolute difference (SAD) value are analyzed with existing method like hexagon, adaptive root pattern algorithm, and diamond search algorithm. Then the hardware parameters like power consumption and maximum operating frequency are measured. The hardware utilization is reduced and the power consumption of the proposed model is diminished to 0.143 W. The maximal operating frequency of the proposed model is 440.470 MHz. The experimental outcomes demonstrate that the proposed motion evaluation approach in HEVC is more effective than existing algorithms.

Performance Analysis of Clock Gated Coordinate Rotation Digital Computer Based Least Mean Square Filter Design for Video Processing Applications

Design of a low power FIR filter has always been an area of intense research concern. Application of Co-ordinate Rotation digital computer (CORDIC) algorithm for designing a low power FIR filter is presented in this paper. CORDIC algorithm helps in the computation of complex trigonometric functions by using shift and adds mechanisms avoiding the need for a separate processor in hardware implementation. The challenge of noise interruption in real time video signal capturing is rejected greatly by using CORDIC LMS filter architecture. Also the area, power, and delay of the LMS filter are reduced to a good extent because of CORDIC multipliers. When compared to the previously discussed filter techniques in various works, the proposed technique shows 21.13% reduction in delay and 90.28% decrease in leakage power. Further improvement in dynamic power savings is obtained through clock gating technique applied to the sequential elements in the circuit, which reduces dynamic power dissipation by 70% from the previous works. The comparative study of benchmark filters with their specifications is presented with a detailed analysis of area, delay, leakage, and dynamic power. The video processing using CORDIC LMS filter is verified with MATLAB R 2021A software. The hardware implementation of the proposed architecture is done on a SPARTAN 3E FPGA kit with Xilinx ISE design suite interface. The design is also verified for delay, area, leakage, and dynamic power using CADENCE with GPDK 180 nm library.

Modified Binary Vedic Multiplication Using Carry Save Adder

This paper presents modified binary Vedic multiplication using carry save adder. The suggested modified binary Vedic multiplication technique is more efficient in terms of delay. The proposed circuit is implemented in Verilog HDL. The Xilinx ISE Design Suite 14.6 is used for circuit synthesis. The simulation done for 4-bit ,8-bit 16-bit multiplication operations. In this paper, the simulation waveforms are shown only for 4-bit and 8-bit multiplication operation based on the modified Vedic multiplication technique using carry save adder. The vedic multiplication method can be extended for a larger bit size. The delay compared with normal multiplication technique.

An efficient field programmable gate array based hardware architecture for efficient motion estimation with parallel implemented genetic algorithm

SummaryThe main idea of this article is to propose a hardware design of block matching (BM) algorithm for an efficient motion estimation (ME) strategy in a field programmable gate array platform based on a parallel implemented genetic algorithm (GA). Easiness and the effectiveness of the BM algorithm while implementing have a major drawback of low quality and computationally cost expensive during the process of ME. Therefore, here in this article, we suggest GA based BM for a quick and cost‐effective computation of motion vectors, without negotiating the quality factor. The ME carried out for various video sequences is implemented by using Xilinx ISE Design Suite 14.1. Delay, time, area, power, PSNR, MSE, SNR, SSIM, and NRMSE are the metrics used for analyzing the performance, and the simulation outcome shows that this parallel implemented BM architecture design shows an exotic improvement in time, quality and in utilization of power on estimating the motion than that of the conventional designs.

Low latency Montgomery multiplier for cryptographic applications

In this modern era, data protection is very important. To achieve this, the data must be secured using either public-key or private-key cryptography (PKC). PKC eliminates the need of sharing key at the beginning of communication. PKC systems such as ECC and RSA is implemented for different security services such as key exchange between sender, receiver and key distribution between different network nodes and authentication protocols. PKC is based on computationally intensive finite field arithmetic operations. In the PKC schemes, modular multiplication (MM) is the most critical operation. Usually, this operation is performed by integer multiplication (IM) followed by a reduction modulo M. However, the reduction step involves a long division operation that is expensive in terms of area, time and resources. Montgomery multiplication algorithm facilitates faster MM operation without the division operation. In this paper, low latency hardware implementation of the Montgomery multiplier is proposed. Many interesting and novel optimization strategies are adopted in the proposed design. The proposed Montgomery multiplier is based on school-book multiplier, Karatsuba-Ofman algorithm and fast adders techniques. The Karatsuba-Ofman algorithm and school-book multiplier recommends cutting down the operands into smaller chunks while adders facilitate fast addition for large size operands. The proposed design is simulated, synthesized and implemented using Xilinx ISE Design Suite by targeting different Xilinx FPGA devices for different bit sizes (64-1024). The proposed design is evaluated on the basis of computational time, area consumption, and throughput. The implementation results show that the proposed design can easily outperform the state of the art

Efficient Implementation of Lightweight MDS Matrix on FPGA

Recently, studying of Maximum Distance Separable (MDS) matrix has become a topic of interest. The MDS matrix is the most important component of the diffusion layer in block ciphers. This paper introduces an optimized, low-cost hardware construction of Galois Field GF(2^8 ) 4×4 MDS matrix. The proposed design is implemented on Field programmable Gate Array (FPGA). The proposed design is synthesized targeting Virtex-7 FPGA using Xilinx ISE Design suite. Xilinx primitives LUT6 and LUT6_2 were used to control exactly the component placement in the design to maintain the minimum occupation area. The pipeline and parallel implementation techniques were used to improve the speed performance. The verification of the functionality of the proposed design has been proved using the ModelSim simulation tool. The synthesis result of the proposed design shows that, the new proposed architecture provides very competitive area and throughput trade-offs. In comparison with other related designs, the proposed design occupies the least area with the minimum time delay. The area of the developed MDS matrix design was significantly reduced, 68 LUT, with high throughput of 21.178 Gbps. The proposed design is a suitable candidate for lightweight cryptographic implementations.

RETRACTED ARTICLE: Implementation of efficient reconfigurable FIR filter with control logic for 5G applications

Filters are used to achieve frequency selectivity on the spectrum of input signal. Due to the stability of finite impulse response (FIR) filters, they are used in most of the applications. In the conventional FIR filters, the frequency band is fixed and cannot be changed once it is designed. Hence, there is a necessity of an FIR filter with auto-adjustment of band width in modern day communication systems like 5G. The design of FIR filter requires more number of filter coefficients to get the desired bandwidth specification. This results in a large slice for field programmable gate array implementation. Here, it proposed a state machine to select different FIR filters with the designated set of coefficients. Each FIR filter is having different set of coefficients, and based on the frequency of the clock signal, the FIR filter is selected and thereby frequency selectivity can be achieved. The proposed method is to implement reconfigurable FIR (RFIR) filter with control logic for auto-adjustment of frequency selections to achieve better band width requirements. The filter order is initially selected as 4 and presented the simulation results. The order of the filter(n) increased to 24 for verifying the bandwidth selection. The proposed architecture is compared with the existing architecture with 16 bits and 11 taps. The proposed method saves 33.5% of look-up-tables (LUTs) compared to the existing methods. Simulation results presented are verified using Xilinx ISE design suite 14.7. The total number of four-input LUTs utilized are 630 for order(n) of the filter 24. Power consumed by the overall design is 195 mW.

Optimized DA-reconfigurable FIR filters for software defined radio channelizer applications

PurposeIn this paper, the authors present different methods for reconfigurable finite impulse response (RFIR) filter design. Distributed arithmetic (DA)-based reconfigurable FIR filter design is suitable for software-defined radio (SDR) applications. The main contribution of reconfiguration is reuse of registers, multipliers, adders and to optimize various parameters such as area, power dissipation, speed, throughput, latency and hardware utilizations of flip-flops and slices. Therefore, effective design of building blocks will be optimized for RFIR filter with all the above parameters.Design/methodology/approachThe modified, direct form register structure of FIR filter contributes the reuse concept and allows utilization of less number of registers and parallel computation operations. The disadvantage of DA and other conventional methods is delay increases proportionally with filter length. This is due to different partial products generated by adders. The usage of adder and multipliers in DA-FIR filter restricts the area and power dissipation because of their complexity of generation of sum and carry bits. The hardware implementation time of an adder can be reduced by parallel prefix adder (PPA) usage based on Ling equation. PPA uses shift-add multiplication, which is a repetitive process of addition, and this process is known as Bypass Zero feed multiplicand in direct multiplication, and the proposed technique optimizes area-power product efficiently. The modified DA (MDA)-based RFIR filter is designed for 64 taps filter length (N). The design is developed by using Verilog hardware description language and implemented on field-programmable gate array. Also, this design validates SDR channel equalizer.FindingsBoth RFIR and SDR are integrated as single system and implemented on Artix-7 development board of XC7A100tCSG324 and exploited the advantages in area-delay, power-speed products and energy efficiency. The theoretical and practical comparisons have been carried out, and the results are compared with existing DA-RFIR designs in terms of throughput, latency, area-delay, power-speed products and energy efficiency, which are improved by 14.5%, 23%, 6.5%, 34.2% and 21%, respectively.Originality/valueThe DA-based RFIR filter is validated using Chipscope Pro software tool on Artix-7 FPGA in Xilinx ISE design suite and compared constraint parameters with existing state-of-art results. It is also tested the filtering operation by applying the RFIR filter on Audio signals for removal of noisy signals and it is found that 95% of noise signals are filtered effectively.

LSTM Cell Implementation on FPGAs

This paper presents and discusses the implementation of an LSTM cell on an FPGA with an activation function inspired by the CORDIC algorithm. The realization is performed using both IEEE754 standard and 32-bit integer numbers. The case with floating-point arithmetic is analyzed with and without DSP blocks provided by the Xilinx design suite. The alternative implementation including the integer arithmetic was optimized for a minimal number of clock cycles. Presented implementation uses xc6slx150t-2fgg900 and achieves high calculations accuracy for both cases.

Design of FFT processor using low power Vedic multiplier for wireless communication

Digital Signal Processing (DSP) is a very significant and active research area. High throughput is a requirement for most wireless communication systems. The critical bottleneck that affects communication ability is the Fast Fourier Transform (FFT), which is the essence of most modulators. Currently, Floating point FFT processors have been used in Radar signal processing, fast convolution, Spectrum estimation and OFDM based modulators/demodulators. Efficient VLSI based architectures are required for real-time FFT processing. The multiplication limits the performance in terms of throughput of FFT. Consequently, there is a need for high speed and low power multiplier architectures with minor truncation error. The present paper presents a modified binary floating-point multiplier using Vedic mathematics and a modification in the previously published Vedic multiplier circuit has been proposed. The entire design has been implemented in Verilog HDL. Synthesis and simulations are done using Xilinx ISE Design Suite 14.5.The performance evaluation in terms of speed and area occupied is compared with the previously reported Vedic multiplier architectures. Using 90 nm technologies, the Power Delay Product (PDF) of the proposed Vedic multiplier gets reduced through KSA by 86.41% compared to the multipliers. The Vedic adder power is reduced by 45.9% when it is compared with the carry look-ahead adder. The overall power delay product is reduced around 55–60% through the FFT processor by using Vedic mathematics.

Design of Low-Power Wallace Tree Multiplier Architecture Using Modular Approach

With the advancement in technology, various designs of multipliers offering low power consumption, high speed and less area have been proposed by many researchers. The main concern of electronic system designers is the energy minimization with the minimum penalty in speed and area for designing portable devices. Recent development focuses on the design of low-power multiplier for applications like biomedical signal processing requiring the least power consumption and delay-tolerant multiplier. This paper proposes a power-efficient design of the Wallace tree multiplier using a power-efficient 7:3 counter consisting of multiplexer and ex-or gates. The maximum power of the multiplier is consumed in the partial product tree reduction, and hence, in the proposed counter-based modular Wallace tree (CBMW) multiplier partial products are reduced using sequential 7:3 counter and the multi-bit addition in a single column reduces the complexity of the multiplier due to improvement in the locality. These proposed changes make design low power and scalable. The hardware utilization is minimum when a single 7:3 counter is used in partial product tree reduction per stage. The proposed multiplier is implemented in the Xilinx ISE design suite 14.7 using Verilog language on Spartan 3E FPGA. The design is also synthesized in Synopsys Design Compiler using 180 nm CMOS technology cell library. The corner analysis of the proposed design is performed in Synopsys PrimeTime, and the design meets all timing specifications. Also, the multiply and accumulate (MAC) unit is designed using the proposed multiplier to demonstrate an application of it. The detailed comparison is performed for 8-bit as well as 16-bit operands, and it shows that the CBMW multiplier gives better delay performance and consumes the least power compared to existing multipliers. It is proved to be an efficient multiplier in terms of Power-Delay Product (PDP). The power consumption of the proposed 16 $$\times $$ 16 multiplier is 88.16 mW and 87.7 $$\mu $$ W for Spartan 3E FPGA and ASIC design for 180 nm technology, respectively. It provides a promising performance for FPGA as well as for the ASIC platform.