Abstract
In this modern era, data protection is very important. To achieve this, the data must be secured using either public-key or private-key cryptography (PKC). PKC eliminates the need of sharing key at the beginning of communication. PKC systems such as ECC and RSA is implemented for different security services such as key exchange between sender, receiver and key distribution between different network nodes and authentication protocols. PKC is based on computationally intensive finite field arithmetic operations. In the PKC schemes, modular multiplication (MM) is the most critical operation. Usually, this operation is performed by integer multiplication (IM) followed by a reduction modulo M. However, the reduction step involves a long division operation that is expensive in terms of area, time and resources. Montgomery multiplication algorithm facilitates faster MM operation without the division operation. In this paper, low latency hardware implementation of the Montgomery multiplier is proposed. Many interesting and novel optimization strategies are adopted in the proposed design. The proposed Montgomery multiplier is based on school-book multiplier, Karatsuba-Ofman algorithm and fast adders techniques. The Karatsuba-Ofman algorithm and school-book multiplier recommends cutting down the operands into smaller chunks while adders facilitate fast addition for large size operands. The proposed design is simulated, synthesized and implemented using Xilinx ISE Design Suite by targeting different Xilinx FPGA devices for different bit sizes (64-1024). The proposed design is evaluated on the basis of computational time, area consumption, and throughput. The implementation results show that the proposed design can easily outperform the state of the art
Highlights
Cryptography has generally been divided into two types, Private-Key Cryptography (P-KC)- symmetric and Public-Key Cryptography (PKC) - asymmetric [1]
The second type of modular multipliers is Interleaved Modular Multiplication (IMM), which can do the reduction during multiplication
We present an efficient MMM that is implemented on modern Field-Programmable Gate Arrays (FPGA) devices
Summary
Cryptography has generally been divided into two types, Private-Key Cryptography (P-KC)- symmetric and Public-Key Cryptography (PKC) - asymmetric [1]. Most of the PKC algorithms implementation need arithmetic operations over a finite field of large characteristics. These operations are modular addition (or subtraction) modular multiplication and modular inversion with large size operands over the finite fields. In RSA, large operands are used for the same security level as compared to ECC. The hardware implementations of ECC provide higher performance if the modular multiplier is designed efficiently. Operations like modular multiplication and inversion are most time and resource-consuming. Cryptographic applications are deployed in several smart devices like mobile phones and Wi-Fi devices These cryptographic applications utilize the varying size of mathematical operands starting from 160-1024 bits. We require operations with varying field sizes depending upon the applications
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