A novel systolic VLSI architecture for fast RSA modular multiplication

Abstract

In this paper, we present a novel systolic VLSI architecture for performing fast modular multiplication in RSA cryptosystem. First, we propose a modified version of Montgomery's modular multiplication algorithm using a precomputed addition result, and then the proposed algorithm is mapped onto linear systolic arrays of processing elements for modular multiplication. Our implementation results have shown that the proposed systolic VLSI architecture is suitable for implementing high performance RSA cryptosystem, compared to conventional Montgomery's algorithm.