WSe2 FETs Research Articles

Impact of grain size on the performance of WSe2 FETs revealed by first-principles calculations

We theoretically investigate the grain size dependence of the mobility of WSe2 FETs, and the experimental results which have been recently reported. A larger grain size (LG) WSe2 has been modeled by a single monolayer WSe2 of infinite length. We model a smaller grain size (SG) WSe2 as a partial monolayer of WSe2 with a zigzag edge WSe2 nanoribbon. Our results show that the step edges of the partial monolayer WSe2 function as electron traps. Moreover, the effective mass of SG WSe2 appears to be much larger than that of LG WSe2 because of hybridization with gap states originating from step edges at the conduction band minimum. These results coincide with recent experiments that show that the on-currents of the SG WSe2 are much lower than those of the LG WSe2. Hence, our calculated results indicate that LG fabrication is essential for advanced large-scale integration (LSI) using WSe2 FETs.

Reliability Improvement of 2-D WSe₂ FETs by Regulating Charge Trapping: An Ab Initio Demonstration

Reliability Improvement of 2-D WSe₂ FETs by Regulating Charge Trapping: An <i>Ab Initio</i> Demonstration

(Invited) 3D Integration of 2D Devices for Neuromorphic Computing

In this presentation, I will delve into the exciting realm of monolithic 3D integration, where emerging 2D FETs take center stage, empowering advanced memory, and logic devices. Furthermore, I will also discuss our work on bio-inspired neuromorphic computing. Notably, our recent breakthroughs have culminated in the successful demonstration of wafer-scale 2-tier and 3-tier 3D integration, utilizing MoS2 and WSe2 FETs as the building blocks. These achievements have paved the way for multifunctional circuits that hold immense promise for the future of electronics. Delving deeper into our research, we have harnessed the potential of 2D materials to design solid-state devices with low power consumption mimicking auditory processing in barn owl, collision avoidance in locust, and probabilistic computing in dragonfly. By combining the power of 2D materials with bio-inspired principles, our work lays a solid foundation for the creation of highly compact and functionally diverse integrated circuits in the revolutionary third dimension. The implications of this technology are far-reaching and hold the potential to shape the future of electronics and computing.

Monolithic three-dimensional integration of complementary two-dimensional field-effect transistors.

The semiconductor industry is transitioning to the 'More Moore' era, driven by the adoption of three-dimensional (3D) integration schemes surpassing the limitations of traditional two-dimensional scaling. Although innovative packaging solutions have made 3D integrated circuits (ICs) commercially viable, the inclusion of through-silicon vias and microbumps brings about increased area overhead and introduces parasitic capacitances that limit overall performance. Monolithic 3D integration (M3D) is regarded as the future of 3D ICs, yet its application faces hurdles in silicon ICs due to restricted thermal processing budgets in upper tiers, which can degrade device performance. To overcome these limitations, emerging materials like carbon nanotubes and two-dimensional semiconductors have been integrated into the back end of silicon ICs. Here we report the M3D integration of complementary WSe2 FETs, in which n-type FETs are placed in tier 1 and p-type FETs are placed in tier 2. In particular, we achieve dense and scaled integration through 300 nm vias with a pitch of <1 µm, connecting more than 300 devices in tiers 1 and 2. Moreover, we have effectively implemented vertically integrated logic gates, encompassing inverters, NAND gates and NOR gates. Our demonstration highlights the two-dimensional materials' role in advancing M3D integration in complementary metal-oxide-semiconductor circuits.

Nonvolatile Reconfigurable Logic Device Based on Photoinduced Interfacial Charge Trapping in van der Waals Gap.

Due to the increasing complexity in miniaturization of electronic devices, reconfigurable field-effect transistors (RFETs) have emerged as a solution. Although the foundational concepts of RFETs have matured over two decades, ongoing breakthroughs are needed to address challenges such as improving the device performance as well as achieving balanced symmetry between n-type and p-type transport modes with long-term stability. Herein, we present a nonvolatile WSe2-based RFET that utilizes photoassisted interfacial charge trapping at the h-BN and SiO2 interface. Unlike typical RFETs with two gate electrodes, our RFETs achieved polarity control with a single operating gate activated exclusively under white-light exposure. The threshold voltage was tunable, ranging from 27.4 (-31.6 V) to 0.9 (+19.5 V), allowing selective activation of n-type (p-type) operation at VGS = 0 V. Additionally, our WSe2-based RFETs show superior repeatability and long-term stability. Leveraging these advantages, various reconfigurable logic circuits were successfully demonstrated, including complementary inverters and switch circuits as well as pull-up and pull-down circuits, highlighting the potential of WSe2 FETs for future advancements of integrated circuits.

Tuning the transport polarity of tungsten diselenide-based n-type FET to p-typeby MoO3 contact doping

Atomically thin tungsten diselenide (WSe2) has emerged as a promising material for next-generation electronic and optoelectronic devices. The surface functionalization of molybdenum trioxide (MoO3) improves the performance of WSe2 FET. The strong hole doping from MoO3 to WSe2 was revealed by measuring the electrical properties of the FET and calculating the electron mobility of WSe2 devices. We demonstrated effective P doping of MoO3 on WSe2 FET devices, and the hole mobility of WSe2 FET devices was improved by 3 orders of magnitude after contact doping with MoO3 at 3.2nm.

Self-Aligned Top-Gate Structure in High-Performance 2D p-FETs via van der Waals Integration and Contact Spacer Doping.

The potential of 2D materials in future CMOS technology is hindered by the lack of high-performance p-type field effect transistors (p-FETs). While utilization of the top-gate (TG) structure with a p-doped spacer area offers a solution to this challenge, the design and device processing to form gate stacks pose serious challenges in realization of ideal p-FETs and PMOS inverters. This study presents a novel approach to address these challenges by fabricating lateral p+-p-p+ junction WSe2 FETs with self-aligned TG stacks in which desired junction is formed by van der Waals (vdW) integration and selective oxygen plasma-doping into spacer regions. The exceptional electrostatic controllability with a high on/off current ratio and small subthreshold swing (SS) of plasma doped p-FETs is achieved with the self-aligned metal/hBN gate stacks. To demonstrate the effectiveness of our approach, we construct a PMOS inverter using this device architecture, which exhibits a remarkably low power consumption of approximately 4.5 nW.

Full two-dimensional ambipolar CFET-like architecture for switchable logic circuits

As the scaling of integrated circuits based on silicon semiconductors becomes increasingly challenging due to the minimum feature size being close to the physical limit, the urgent demand for alternative strategies has fuelled the rapid growth of techniques and material innovations. Here, we report on the fabrication of vertically stacked ambipolar complementary field-effect transistor that is fully composed of two-dimensional materials of WSe2/h-BN/graphene/h-BN/WSe2 heterostructures. The ambipolar feature of the top and bottom WSe2 FET enables a switchable inverter behavior with a favorable voltage gain of up to 75, which can work in both the first and third quadrants. Based on the switchable characteristics, a large voltage swing circuit for single photon avalanche detectors is proposed without any bulky negative-voltage components. This work could open a new pathway for future two-dimensional electronics and ultimate monolithic 3D high-density integration circuits.

Toward Unusual-High Hole Mobility of p-Channel Field-Effect-Transistors.

The relative low hole mobility of p-channel building block device challenges the continued miniaturization of modern electronic chips. Metal-semiconductor junction is always an efficient strategy to control the carrier concentration of channel semiconductor, benefiting the carrier mobility regulation of building block device. In this work, complementary metal oxide semiconductor (CMOS)-compatible metals are selected to deposit on the surface of the important p-channel building block of GaSb nanowire field-effect-transistors (NWFETs), demonstrating the efficient strategy of hole mobility enhancement by metal-semiconductor junction. When deposited with lower work function metal of Al, the peak hole mobility of GaSb NWFET can be enhanced to as high as ≈3372 cm2 V-1 s-1 , showing three times than the un-deposited one. The as-studied metal-semiconductor junction is also efficient for the hole mobility enhancement of other p-channel devices, such as GaAs NWFET, GaAs film FET, and WSe2 FET. With the enhanced mobility, the as-constructed CMOS inverter shows good invert characteristics, showing a relatively high gain of ≈18.1. All results may be regarded as important advances to the next-generation electronics.

A comparative study of charge trapping effect in p-type MoTe2 and WSe2 FETs using pulsed current–voltage measurements

P-type semiconductors are indispensable for achieving complementary metal oxide semiconductor and integrated circuits based on two-dimensional (2D) semiconductors, and tungsten diselenide (WSe2) and molybdenum ditelluride (MoTe2) are the promising channel materials for PMOS. In this work, we report on the charge trapping effects on hysteretic behavior and field-effect mobility (μ FE) of the p-type WSe2 and MoTe2 FETs using fast pulsed current–voltage (I–V) measurements. The hysteresis is reduced by nearly 98% via ramped pulsed measurements, and μ FE is significantly enhanced via single pulse measurements by minimizing the charge trapping. Moreover, WSe2 FETs are found to be more susceptible to the charge trapping effects compared with MoTe2 FETs; WSe2 FETs exhibit more pronounced enhancement of μ FE and reduction of hysteresis. The intrinsic electrical characteristics of p-type 2D FETs under minimized charge trapping conditions can be investigated using the pulsed I–V characterizations.

Charge transfer doping with an organic layer to achieve a high-performance p-type WSe2 transistor

A WSe2 FET with a top DNTT layer was fabricated and exhibited remarkable performances: decent on–off switching and high hole mobility. The deposition of DNTT on the WSe2 induced the charge transfer from DNTT to WSe2 and, thus, p-doping of the latter.

(Invited) Vertical Integration through Direct Growth of Van Der Waals Materials

The integration of novel logic and memory devices, fabricated from van der Waals materials, into CMOS process flows with a goal of improving system-level Energy-Delay-Product (EDP) for data abundant applications will be discussed. Focusing on materials growth and integration techniques that utilize non-equilibrium, kinetically restricted strategies, coupled with in-situ characterization, enables the realization of atomic configurations and materials that are challenging to make but once attained, display enhanced and unique properties. These strategies become necessary for most future technologies where thermal budgets are constrained and conformal growth over selective areas and 3-dimensional structures are required.In this work, we demonstrate the high-quality MBE heterostructure growth of various layered materials by van der Waals epitaxy (VDWE). The coupling of different types of van der Waals materials including transition metal dichalcogenide thin films (e.g., WSe2, WTe2, HfSe2), helical Te thin films, and topological insulators (e.g., Bi2Se3) allows for the fabrication of novel electronic devices that take advantage of unique quantum confinement and spin-based characteristics. We demonstrate how the van der Waals interactions allow for heteroepitaxy of significantly lattice-mismatched materials without strain or misfit dislocations. Yet, at the same time, the VDW interactions are strong enough to cause rotational alignment between the epi-layer and the substrate, which plays a key role in the formation of grain boundaries. We will discuss TMDs, Te, and TIs grown on atomic layer deposited (ALD) high-k oxides on a Si platform as well as flexible substrates and demonstrate field-effect transistors with back-end-of-line compatible fabrication temperatures (<450 °C).As an example, the room temperature I-V curves of WSe2 FETs grown by MBE on ALD-grown amorphous Al2O3 indicate strong ambipolar conduction with electron and hole ON currents reaching ~25 and 15 µA/µm, respectively and ON/OFF ratios exceeding 104. Hole mobilities of ~50 cm2/V-s are achieved. The subthreshold swing in the hole branch is ~230 mV/dec over three decades of ID , suggesting an immobile charge density of ~8 x 1012 cm-2. Esaki tunnel junctions in WSe2 FETs are also demonstrated with 40 nm channel length. A back-gate is employed which makes the negative differential resistance (NDR) gate-tunable at temperatures up to 140 K and a maximum peak-to-valley current ratio (PVCR) of 3.5 at T = 110 K. When compared to previous reports for WSe2, the fabricated Esaki junctions provide increased PVCRs, from ~2 to 3.5, 100x higher peak currents, from ~pA/µm to ~nA/µm levels, and a significant reduction in the peak voltage, VP , from 1.5 to 0.2 V, as should be expected for tunnel diodes.High performance transistors made from helical Te with field-effect mobilities as high as 700 cm2/V-s have also been demonstrated. These devices are fabricated from Te needle-like structures directly grown on thermal SiO2 on a back-gated structure at 120 °C. The achievement of high-mobility transistor channels at BEOL compatible processing temperatures shows the potential for integrating van der Waals materials into CMOS process flows.In summary, we have demonstrated the growth of a variety of van der Waals materials directly grown even on amorphous oxides at BEOL compatible temperatures. Using novel techniques to improve the crystal quality at these low temperatures has enabled the demonstration of devices that can be intergrated above high-performance circuits and metal levels. TFTs and tunnel devices in particular have been demonstrated with outstanding performance suggesting a path forward for heterogeneous integration and improved systems level performance.This work is supported in part by NEWLIMITS, a center in nCORE, a Semiconductor Research Corporation (SRC) program sponsored by NIST through award number 70NANB17H041. This work is also supported by the National Science Foundation under awards 1917025 and 1921818.

Selective Electron or Hole Conduction in Tungsten Diselenide (WSe2) Field-Effect Transistors by Sulfur-Assisted Metal-Induced Gap State Engineering

For semiconductor industry to replace silicon CMOS integrated circuits by 2-D semiconductors or transition metal dichalcogenides (TMDs), TMD-based n-FETs as well as p-FETs having performance better than Si FETs are a must. While a lot of literature demonstrates n-channel characteristics, the major roadblocks in the realization of TMD-based CMOS integrated circuit are the lack of approach to realize p-channel transistors having performance comparable to n-channel transistors, all realized over the same TMD substrate. To address this, we propose a new technique by engineering WSe2/metal interface to realize WSe2-based high-performance p- and n-channel transistors and therefore unveil its potential toward CMOS-integrated technology. The technique involves a dry process, based on the chemistry between the sulfur atom and WSe2 surface, that induces unique metal-induced gap states in the source/drain (S/D) contact area, which causes improved hole (electron) injection when Cr (Ni) as S/D metal was used. This has enabled the controlled realization of high-performance WSe2 FETs with desired polarity (N, P, or ambipolar), which solely depends on the contact metal used and contact engineering (CE)/surface engineering. Fundamental investigations on the effect of the proposed CE on metal-WSe2 interface revealed interesting and counter-intuitive facts, which very well corroborate with experimental observations.

Enhancing Electrical and Contact Properties of WSe2 ­­field-Effect Transistors Via Vacuum-Annealed Pt-W Alloy Contacts

Two-dimensional (2D) materials have been extensively studied as one of the promising post-silicon materials for nano-sized field effect transistors to overcome physical limits of Si-based electronic devices. Semiconducting transition metal dichalcogenides (TMDs) have been studied as attractive candidates with sizeable band structure, in contrast to graphene with zero band gap limiting its implementation into electronics due to large off-currents and low drain-current modulation. Among all, tungsten diselenide (WSe2) has attracted attention as a p-type conducting material with its high current on/off ratio, hole mobility, and environmental stability. Despite the superior electrical properties of WSe2, difficulty in forming of a stable Ohmic contact with a low contact resistance has posed a significant limitation in fabricating WSe2-based devices. It creates van der Waals (vdW) gaps with contact metal and additional tunneling barrier, which increases contact resistance and affects device performance. Efforts have been made to reduce contact resistance such as by work function engineering and charge transfer methods employing various novel technical strategies. However, such approaches still need industrial fabrication compatibility and environmental stability. In this work, a simple one-step vacuum annealing was used to address vdW gaps and reduce contact resistance. Thermal annealing is extensively incorporated in conventional compound semiconductor fabrication process to facilitate alloying or inter-diffusion of metal to semiconductors and enhance contact properties. Plus, thermal annealing can eliminate interlayer residues originated from the repeated exfoliation and dry transfer processes, which would deteriorate electrical contact between metals and TMDs. Herein, few-layered WSe2 was transferred on to platinum (Pt) electrodes with high work function (>5 eV) to facilitate hole injection. Effects of vacuum annealing on the performance of WSe2 FETs were then investigated. With improved contact properties from the removal of interlayer residues, the device performance including on-current density, hole mobility, and current on/off ratio enhanced up to the temperature of 650 ℃. Especially, p-type conduction was greatly improved after vacuum-annealed at 600 ℃, confirmed by selenium vacancy-aided formation of interlayer PtxW1-x alloy. The alloyed contacts occupied between WSe2 and Pt played a role in improving contact properties and lowering contact resistance. The device performance started to deteriorate when vacuum-annealed above 650 ℃, which is attributed to thermal degradation of WSe2 channel from high annealing temperature. Our work would further pave the way for achieving methods in fabricating a reliable TMDs based devices. Details will be discussed at the presentation. Figure 1

Ohmic Contact in 2D Semiconductors via the Formation of a Benzyl Viologen Interlayer

AbstractThe fabrication of a polymeric Ohmic contact interlayer between a metal and a 2D material using solution‐processed benzyl viologen (BV) is reported here. Predoping of the polymer alters the contact surface to obtain electron‐doped materials with ultrahigh work functions that significantly enhance the current density across the contact and reduce the contact resistance and Schottky barrier height. The fabrication of solution‐processed polymeric contacts for the preparation of high mobility MoS2, WSe2, MoTe2, and BP (black phosphorous) FETs with significantly lowered contact resistance is demonstrated. Ohmic contacts are achieved and produce 3‐, 700‐, 3000‐, and 17‐fold increases in electron mobilities, respectively, when the bottom gate voltage is 10 V compared to those respective materials alone. Ambipolar and p‐type 2D material based FETs could, therefore, be transformed into n‐type FETs. Most importantly, the devices exhibit excellent stability in both ambient and vacuum.

Hysteresis Dynamics in Double-Gated n-Type WSe2 FETs With High-k Top Gate Dielectric

We propose double-gated n-type WSe2 FETs with low leakage, low hysteresis top gate high-k dielectric stack. The top gate dielectric layer is deposited by HfO2 ALD on an Al2O3 seed layer obtained from the evaporation and oxidation by air exposure of a 1.5 nm Al layer. When operated under back gate control, the fabricated WSe2 FETs behave as n-type enhancement transistors with ON/OFF current ratios exceeding 6 orders of magnitude and a ON current close to 1 $\mu \text{A}/\mu \text{m}$ at a drain bias of 100 mV. An applied negative top gate bias determines a much steeper turn-on of the back gated transfer characteristic and a reduction of the observed hysteresis. Top gate devices behave as n-type depletion FETs, reaching a ION/IOFF ratio larger than 106 under positive bias applied to the back gate. The electron mobility, extracted using the Y-function method, was estimated to be 22.15 cm2V−1s−1 under a drain bias of 1 mV. We characterize the hysteresis dynamics in our devices, demonstrating a substantial improvement with respect to comparable top gated MoS2 FETs.

The device level modulation of carrier transport in a 2D WSe2 field effect transistor via a plasma treatment.

Tungsten diselenide (WSe2) has received significant attention because it shows the pristine ambipolar property arising from the Fermi level located near the midgap and can be converted to uni-polar form. In this study, we observe the formation of tungsten oxide (WOx) on the WSe2 surface after oxygen plasma treatment and show that the p-type WOx dopes WSe2. In our devices that underwent plasma treatment, it was interesting to find a strong correlation between the changes in the work function of WSe2 and a gold electrode, and the channel and contact resistances. The channel resistance changes very sensitively at a rate of 64 meV per dec with the increase in the WSe2 channel work function, which is close to the thermal limit; this indicates the defect-free oxidized WSe2 channel. The carrier transport in the oxidized WSe2 FET is shown to change to a high performance p-type device with greatly reduced channel and contact resistances with the increase in the plasma oxidation time.

Analysis of asymmetrical hysteresis phenomena observed in TMD-based field effect transistors

To realize field effect transistors with multi-layered MoS2 and WSe2 (hereafter denoted as MoS2 FET and WSe2 FET), many device instability problems should be surmounted, such as the hysteresis generation of the devices. In order to clarify the mechanism of the asymmetrical hysteresis phenomena observed in the transfer characteristics of the MoS2 and WSe2 FET, the temperature dependencies of their characteristics are analyzed. Based on these analyses, it can be concluded that donor-like traps present in both the SiO2/MoS2 interface and the MoS2 bulk in multi-layered MoS2 FETs, and that acceptor-like traps present in both the SiO2/WSe2 interface, and the WSe2 bulk in multi-layered WSe2 FETs. Furthermore, based on the chemical analyses and the arguments presented in previous studies, we propose that the sulfur vacancy (SV) is the origin of donor-like traps present in MoS2, and the tungsten vacancy (TV) is the origin of acceptor-like traps present in WSe2. This work may provide a potential clue to overcome many practical problems for realization of the transition metal dichalcogenides (TMDs) based FETs.

A physically based compact I–V model for monolayer TMDC channel MOSFET and DMFET biosensor

In this work, a compact transport model has been developed for monolayer transition metal dichalcogenide (TMDC) channel MOSFET. The analytical model solves the Poisson’s equation for the inversion charge density to get the electrostatic potential in the channel. Current is then calculated by solving the drift–diffusion equation. The model makes gradual channel approximation to simplify the solution procedure. The appropriate density of states obtained from the first principle density functional theory simulation has been considered to keep the model physically accurate for monolayer TMDC channel FET. The outcome of the model has been benchmarked against both experimental and numerical quantum simulation results with the help of a few fitting parameters. Using the compact model, detailed output and transfer characteristics of monolayer WSe2 FET have been studied, and various performance parameters have been determined. The study confirms excellent ON and OFF state performances of monolayer WSe2 FET which could be viable for the next generation high-speed, low power applications. Also, the proposed model has been extended to study the operation of a biosensor. A monolayer MoS2 channel based dielectric modulated FET is investigated using the compact model for detection of a biomolecule in a dry environment.

FETs on 2-D Materials: Deconvolution of the Channel and Contact Characteristics by Four-Terminal Resistance Measurements on WSe2Transistors

FETs made on 2-D semiconductors, typically without degenerate doping at the contacts, have a significant Schottky junction (SJ) resistance, which complicates transistor analysis. This paper evaluates the effect of the contact resistance on the 2-D-material FET characteristics through four-terminal (4-T) resistance measurements on WSe2 FETs, which allow studying the channel and contacts characteristics separately. Apart from showing the nonnegligibility of contact resistance, this paper enables a finer understanding of commonly observed phenomena, such as transistor performance improvement with dielectric-encapsulation is observed to have a stronger effect on the contact than the channel; the resistance of the forward-biased SJ is observed to be not negligible, but comparable to that of the reverse-biased junction; at biases commonly referred to as “low-bias,” the WSe2 FET resistance could be dominated by the contacts; and pinchoff can be observed at relatively lower current levels, being related to the channel-contact resistance ratio rather than their magnitudes. In the devices where true channel pinchoff can be verified, a correlation emerges between current saturating behavior and asymmetry in the output characteristics with respect to the drain–source bias polarity, a feature that may serve as a guide toward interpreting standard FET output characteristics in 2-D materials.