Abstract

The integration of novel logic and memory devices, fabricated from van der Waals materials, into CMOS process flows with a goal of improving system-level Energy-Delay-Product (EDP) for data abundant applications will be discussed. Focusing on materials growth and integration techniques that utilize non-equilibrium, kinetically restricted strategies, coupled with in-situ characterization, enables the realization of atomic configurations and materials that are challenging to make but once attained, display enhanced and unique properties. These strategies become necessary for most future technologies where thermal budgets are constrained and conformal growth over selective areas and 3-dimensional structures are required.In this work, we demonstrate the high-quality MBE heterostructure growth of various layered materials by van der Waals epitaxy (VDWE). The coupling of different types of van der Waals materials including transition metal dichalcogenide thin films (e.g., WSe2, WTe2, HfSe2), helical Te thin films, and topological insulators (e.g., Bi2Se3) allows for the fabrication of novel electronic devices that take advantage of unique quantum confinement and spin-based characteristics. We demonstrate how the van der Waals interactions allow for heteroepitaxy of significantly lattice-mismatched materials without strain or misfit dislocations. Yet, at the same time, the VDW interactions are strong enough to cause rotational alignment between the epi-layer and the substrate, which plays a key role in the formation of grain boundaries. We will discuss TMDs, Te, and TIs grown on atomic layer deposited (ALD) high-k oxides on a Si platform as well as flexible substrates and demonstrate field-effect transistors with back-end-of-line compatible fabrication temperatures (<450 °C).As an example, the room temperature I-V curves of WSe2 FETs grown by MBE on ALD-grown amorphous Al2O3 indicate strong ambipolar conduction with electron and hole ON currents reaching ~25 and 15 µA/µm, respectively and ON/OFF ratios exceeding 104. Hole mobilities of ~50 cm2/V-s are achieved. The subthreshold swing in the hole branch is ~230 mV/dec over three decades of ID , suggesting an immobile charge density of ~8 x 1012 cm-2. Esaki tunnel junctions in WSe2 FETs are also demonstrated with 40 nm channel length. A back-gate is employed which makes the negative differential resistance (NDR) gate-tunable at temperatures up to 140 K and a maximum peak-to-valley current ratio (PVCR) of 3.5 at T = 110 K. When compared to previous reports for WSe2, the fabricated Esaki junctions provide increased PVCRs, from ~2 to 3.5, 100x higher peak currents, from ~pA/µm to ~nA/µm levels, and a significant reduction in the peak voltage, VP , from 1.5 to 0.2 V, as should be expected for tunnel diodes.High performance transistors made from helical Te with field-effect mobilities as high as 700 cm2/V-s have also been demonstrated. These devices are fabricated from Te needle-like structures directly grown on thermal SiO2 on a back-gated structure at 120 °C. The achievement of high-mobility transistor channels at BEOL compatible processing temperatures shows the potential for integrating van der Waals materials into CMOS process flows.In summary, we have demonstrated the growth of a variety of van der Waals materials directly grown even on amorphous oxides at BEOL compatible temperatures. Using novel techniques to improve the crystal quality at these low temperatures has enabled the demonstration of devices that can be intergrated above high-performance circuits and metal levels. TFTs and tunnel devices in particular have been demonstrated with outstanding performance suggesting a path forward for heterogeneous integration and improved systems level performance.This work is supported in part by NEWLIMITS, a center in nCORE, a Semiconductor Research Corporation (SRC) program sponsored by NIST through award number 70NANB17H041. This work is also supported by the National Science Foundation under awards 1917025 and 1921818.

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