Worst-case Stress Research Articles

On-chip electrostatic discharge protections in advanced CMOS technologies

In this paper several on-chip electrostatic discharge (ESD) protections for inputs, outputs and supply pins are discussed. By comparing different structures, insight has been attained in the most important parameters determining the ESD sensitivity, and optimal protections for the Human Body Model (HBM) which could be selected. In addition the test method as prescribed by the Mil-Std 883C Method 3015.7 is discussed more into detail, leading to the concept of using a supply protection for improving the ESD performance of inputs/outputs (I/Os). For input protections the performance of the lateral silicon controlled rectifier (SCR) structure is found to be superior to the behaviour of the classical thick oxide protection, the minimum failure voltage of the former being 6000 V. Several alternatives for CMOS outputs are also presented. A comparison between the “waffle” layout and the more classical ladder layout concerning the ESD performance is made. A minimum failure voltage of 1750 V for stressing the output vs the ground for both polarities has been seen on one of our output structures. However, the output failure voltage can be increased by using a good supply protection, providing a parallel discharge path. The concept of using a supply protection for achieving a better ESD hardness is highlighted in this paper. An output of a ring oscillator with a thick oxide supply protection did not fail up to 2000 V for a worst case stress, and using a SCR supply protection with an optimised output layout still should result in a better ESD hardness.

Gate-induced drain leakage current degradation and its time dependence during channel hot-electron stress in n -MOSFETs

The effects of channel hot-electron stress on the gate-induced drain leakage current (GIDL) in n-MOSFETs with thin gate oxides have been studied. It is found that under worst case stress, i.e. a high density of generated interface states Delta D/sub it/, the enhanced GIDL exhibits a significant drain voltage dependence. Whereas Delta D/sub it/ increases significantly the leakage current at low V/sub d/, it has minor effects at high V/sub d/. On the other hand, the electron trapping was found to increase the leakage current rather uniformly over both low and high V/sub d/ regions. In addition, GIDL degradation can be expressed as a power law time dependence (i.e. Delta I/sub leak/=A.t/sup n/), and the time dependence value n varies according to the dominant damage mechanism (i.e. electron trapping against Delta D/sub it/), similar to that reported for on-state device degradation.

A model for AC hot-carrier degradation in n-channel MOSFETs

A recently developed model for AC hot-carrier lifetimes is shown to be valid for typical and worst-case stress waveforms found in CMOS circuits. Three hot-carrier damage mechanisms are incorporated into the model: interface states created at low and medium gate voltages, oxide electron traps created at low gate voltages, and oxide electron traps created at high gate voltages. It is shown that the quasi-static contributions of these three mechanisms fully account for hot-carrier degradation under inverterlike AC stress. No transient effects are required to explain AC stress results, at least for frequencies up to 1 MKz.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The relationship between gate bias and hot-carrier-induced instabilities in buried- and surface-channel PMOSFETs

For accurate predictions of device reliability with respect to hot-carrier effects, it is necessary to establish worst-case stress bias conditions. Detailed measurements of hot-carrier-induced instabilities in short-channel PMOSFETs have revealed that stress gate bias conditions corresponding to peak gate currents result in maximum shifts in device parameters. However, for some parameters, notably those measured at low drain bias, comparable shifts are observed for stress gate bias conditions that correspond to peak substrate currents. These observations are valid for both buried-channel (n-type polysilicon gate) and surface-channel (p-type polysilicon gate) PMOSFETs. An interpretation of these results based on the generation of tapped oxide charge and interface traps is proposed. >

Internal Responses of a Complex Satellite Model to Two Electron-Induced Discharge Simulation Techniques

A complex two-thirds scale electromagnetic model of the P78-2 (SCATHA) satellite has been constructed and tested using simulations of two different aspects of an electron-induced discharge (EID). These are a MIL-STD 1541 arc injection which simulates a punchthrough or flashover discharge and capacitive direct injection (CDI) which simulates charge blowoff which accompanies the breakdown. The results show that CDI generally produces larger internal responses per ampere of drive current, by factors of two to almost one hundred, than does arc injection except when the arc point is closely coupled to the measurement point, e.g., on the solar array. Then arc injection can produce greater responses. It was also found that, because of their diode nature, the response of the solar arrays may be dependent on the drive current polarity. The scale model test results were used to estimate the P78-2 responses to both arc injection and CDI. These data confirm the observation that no upsets occurred during arc injection tests of the P78-2. However, CDI tests on the model indicate that some critical circuits in the spacecraft may suffer upsets for blowoff discharges involving dielectric areas of ~100 cm2. The limited on-orbit data presently available appears to be consistent with predictions based on the model tests. The program results to date suggest two changes to the MIL-STD 1541 tests: (1) CDI should be added as a more meaningful EID worst-case stress, and (2) proper polarity of injection (especially to solar arrays) should be considered.