On-chip electrostatic discharge protections in advanced CMOS technologies

Abstract

In this paper several on-chip electrostatic discharge (ESD) protections for inputs, outputs and supply pins are discussed. By comparing different structures, insight has been attained in the most important parameters determining the ESD sensitivity, and optimal protections for the Human Body Model (HBM) which could be selected. In addition the test method as prescribed by the Mil-Std 883C Method 3015.7 is discussed more into detail, leading to the concept of using a supply protection for improving the ESD performance of inputs/outputs (I/Os). For input protections the performance of the lateral silicon controlled rectifier (SCR) structure is found to be superior to the behaviour of the classical thick oxide protection, the minimum failure voltage of the former being 6000 V. Several alternatives for CMOS outputs are also presented. A comparison between the “waffle” layout and the more classical ladder layout concerning the ESD performance is made. A minimum failure voltage of 1750 V for stressing the output vs the ground for both polarities has been seen on one of our output structures. However, the output failure voltage can be increased by using a good supply protection, providing a parallel discharge path. The concept of using a supply protection for achieving a better ESD hardness is highlighted in this paper. An output of a ring oscillator with a thick oxide supply protection did not fail up to 2000 V for a worst case stress, and using a SCR supply protection with an optimised output layout still should result in a better ESD hardness.