Worst-case Stress Research Articles

Stress-based and robust topology optimization for thermoelastic multi-material periodic microstructures

To take advantage of multi-material additive manufacturing technology using mixtures of metal alloys, a topology optimization framework is developed to synthesize high-strength spatially periodic metamaterials possessing unique thermoelastic properties. A thermal and mechanical stress analysis formulation based on homogenization theory is developed and is used in a regional scaled aggregation stress constraint method. Since specific load cases are not always known beforehand, a method of worst-case stress minimization is also included to efficiently address load uncertainty. It is shown that the two stress-based techniques lead to thermal expansion properties that are highly sensitive to small changes in material distribution and composition. To resolve this issue, a uniform manufacturing uncertainty method is utilized which considers variations in both geometry and material mixture. Test cases of high stiffness, zero thermal expansion, and negative thermal expansion microstructures are generated, and the stress-based and manufacturing uncertainty methods are applied to demonstrate how the techniques alter the optimized designs. Large reductions in stress are achieved while maintaining robust strength and thermal expansion properties.

On the Trap Locations in Bulk FinFETs After Hot Carrier Degradation (HCD)

In this brief, typical locations of the interface and oxide traps generated by the hot carrier degradation (HCD) in FinFETs are studied with experiments and “atomistic” TCAD simulations under the worst case stress conditions. The typical round-Fin locations of different types of traps are analyzed by comparing the experimentally extracted results with the calibrated TCAD simulations. Then, the traps’ different impacts on HCD variations in both forward and reverse bias modes are employed to disclose the typical lateral locations of different traps. The results suggest that for both n- and p-type of FinFETs under the worst case stress conditions, the interface traps and oxide traps (type 1) are mainly distributed in the midchannel region closer to the source side on the Fin side, whereas oxide traps (type 2) are mainly distributed in the midchannel region closer to the drain side on the Fin top. Therefore, the two types of oxide traps originate in the different generation locations but may share the same atomistic structures in the same device. The results are helpful to the physical understandings of HCD in the FinFET technology.

Stress-Constrained Design of Functionally Graded Lattice Structures With Spline-Based Dimensionality Reduction

Abstract This paper presents a computationally tractable approach for designing lattice structures for stiffness and strength. Yielding in the mesostructure is determined by a worst-case stress analysis of the homogenization simulation data. This provides a physically meaningful, generalizable, and conservative way to estimate structural failure in three-dimensional functionally graded lattice structures composed of any unit cell architectures. Computational efficiency of the design framework is ensured by developing surrogate models for the unit cell stiffness and strength as a function of density. The surrogate models are then used in the coarse-scale analysis and synthesis. The proposed methodology further uses a compact representation of the material distribution via B-splines, which reduces the size of the design parameter space while ensuring a smooth density variation that is desirable for manufacturing. The proposed method is demonstrated in compliance with minimization studies using two types of unit cells with distinct mechanical properties. The effects of B-spline mesh refinement and the presence of a stress constraint on the optimization results are also investigated.

Hot-Carrier-Induced Degradation and Optimization for Lateral DMOS With Split-STI-Structure in the Drift Region

The lateral double-diffusion MOS with split shallow trench isolation structure (split-STI LDMOS) in the drift region has been investigated under two hotcarrier stresses including the maximum bulk current stress (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bulkmax</sub> ) and maximum operating gate stress (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gmax</sub> ). For the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bulkmax</sub> stress condition, the main damage point causing the degradation of RON is found at the STI corner closest to the source with the interface state generation. In addition, the hot hole injection is found at the edge of the shrinking poly-gate region. For the V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">gmax</sub> stress condition, the main damage point causing the degradation of R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> is found at the two STI corners with interface state generation. Due to the more serious degradation of R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> , the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">bulkmax</sub> stress condition is regarded as the worst-case stress condition. The novel structure with the H-shape STI in the drift region is proposed. It is demonstrated that the H-shape STI structure is effectively helpful to alleviate the hot-carrier degradation without altering the tradeoff between the OFF-state breakdown voltage and specific ON-resistance.

Electric Car Chassis for Shell Eco Marathon Competition: Design, Modelling and Finite Element Analysis

The increasing demand for energy efficient electric cars, in the automotive sector, entails the need for improvement of their structures, especially the chassis, because of its multifaceted role on the vehicle dynamic behaviour. The major criteria for the development of electric car chassis are the stiffness and strength enhancement subject to mass reduction as well as cost and time elimination. Towards this direction, this work indicates an integrated methodology of developing an electric car chassis considering the modeling and simulation concurrently. The chassis has been designed in compliance with the regulations of Shell Eco Marathon competition. This methodology is implemented both by the use of our chassis load calculator (CLC) model, which automatically calculates the total loads applied on the vehicle’s chassis and by the determination of a worst case stress scenario. Under this extreme stress scenario, the model’s output was evaluated for the chassis design and the FEA method was performed by the pre-processor ANSA and the solver Ansys. This method could be characterized as an accurate ultrafast and cost-efficient method.

Multiple Defects Cause Degradation After High Field Stress in AlGaN/GaN HEMTs

Gate and drain bias dependences of hot carrier degradation are evaluated for AlGaN/GaN HEMTs fabricated via two different process methods. Both positive and negative threshold voltage $V_{\mathbf{th}}$ shifts are observed for each device type, depending on the mode and duration of the stress, indicating the presence of significant densities of donor-like and acceptor-like traps. Worst-case stress bias for transconductance degradation is the “ON” state for both device types. We find that transconductance degradation provides a more effective parameter to monitor defect buildup than $V_{\mathbf{th}}$ shifts, and that a single worst-case stressing bias condition cannot be defined for all varieties of AlGaN/GaN HEMTs. Low-frequency noise measurements versus temperature assist the identification of defects responsible for the observed degradation. Defect dehydrogenation and oxygen impurity centers are found to be particularly significant to the response of these devices.

Worst-case stress relief for microstructures

Additive fabrication technologies are limited by the types of material they can print: while the technologies are continuously improving, still only a relatively small discrete set of materials can be used in each printed object. At the same time, the low cost of introducing geometric complexity suggests the alternative of controlling the elastic material properties by producingmicrostructures, which can achieve behaviors significantly differing from the solid printing material. While promising results have been obtained in this direction, fragility is a significant problem blocking practical applications, especially for achieving soft material properties: due to stress concentrations at thin joints, deformations and repeated loadings are likely to cause fracture.We present a set of methods to minimize stress concentrations in microstructures by evolving their shapes. First, we demonstrate that the worst-case stress analysis problem (maximizing a stress measure over all possible unit loads) has an exact solution for periodic microstructures. We develop a new, accurate discretization of the shape derivative for stress objectives and introduce a low-dimensional parametric shape model for microstructures. This model supports robust minimization of maximal stress (approximated by anLpnorm with highp) and an efficient implementation of printability constraints. In addition to significantly reducing stresses (by a typical factor of 5X), the new method substantially expands the range of effective material properties covered by the collection of structures.

A general framework for robust topology optimization under load-uncertainty including stress constraints

We present a worst-case approach for topology optimization under load-uncertainty based on a general problem formulation involving maxima of quadratic functions of an uncertain load vector as both objective and constraints. The problem is reformulated as a non-linear semi-definite program which can be solved efficiently. An important special case of the general problem formulation is worst-case compliance minimization under worst-case stress constraints which is illustrated by numerical examples.

Countercyclical Capital Regime: A Proposed Design and Empirical Evaluation

Motivated by the Great Recession in 2008, countercyclical capital regimes are now being considered by financial regulators. This paper provides a methodology on structuring a countercyclical capital requirement to achieve the goal of determining, at the time of acquisition, an amount of capital sufficient to survive a plausible but worst case stress period, in essence to fully capitalize the asset at acquisition.

Worst Case Stress Conditions for Hot Carrier Degradation with Technology Nodes from 0.35µm to 45nm

The worst case stress conditions for hot carrier degradation have been investigated in detail at the devices fabricated with CMOS technologies from 0.35µm to 45nm. In nMOSFETs with long channel devices (L>0.18µm), Vg at Ibmax and the lowest temperature is the worst case condition; For short channel devices (0.13 µm ≤ L ≤ 0.18μm), Vg @ Ibmax and Vg=Vd stress conditions result in comparable hot carrier damage; For the very short channel transistors (L<0.13µm), the worst case stress condition has been found to be Vg=Vd instead of Vg@Ibmax. In this case, the higher temperature will induce worse hot carrier degradation. In pMOSFETs, the stress conditions Vg@Igmax is the worst case condition for the long channel devices (L≥0.35µm). As the channel length scaled to sub-0.25µm, the worst case stress condition shifts from Vg@Igmax to VG = VD.

FinFET SRAM Cell Optimization Considering Temporal Variability Due to NBTI/PBTI, Surface Orientation and Various Gate Dielectrics

This paper analyzes the impacts of intrinsic process variations and negative bias temperature instability (NBTI)/positive BTI (PBTI)-induced time-dependent variations on the stability/variability of 6T FinFET static random access memory (SRAM) cells with various surface orientations and gate dielectrics. Due to quantum confinement, (110)-oriented pull down n-channel FETs with fin line-edge roughness (LER) show larger Vread,0 and Vtrip variations, thus degrading READ static noise margin (RSNM) and its variability. Pull-up p-channel FETs with fin LER that are (100)-oriented show larger Vwrite,0 and Vtrip variations, hence degrade the variability of WRITE SNM. The combined effects of intrinsic process variations and NBTI/PBTI-induced statistical variations have been examined to optimize the FinFET SRAM cells. Worst-case stress scenario for SNM stability/variability is analyzed. With the presence of both NBTI and PBTI in high-fe metal-gate FinFET SRAM, the RSNM suffers significant degradation as Vread,0 increases, whereas Vtrip simultaneously decreases. Variability comparisons for FinFET SRAM cells with different gate stacks (SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> and SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ) are also examined. Our paper indicates that the consideration of NBTI/PBTI-induced temporal variation changes the optimal choice of FinFET SRAM cell surface orientations in terms of the μ/σ ratio in RSNM.

Gate voltage dependence on hot carrier degradation at an elevated temperature in a device with ultrathin silicon oxynitride

The effects of hot carrier stress (HCS) at elevated temperature on a device with ultrathin silicon oxynitride have been investigated. It was shown that the degradation of the device was more significant at elevated temperature compared with at room temperature. This behavior attributed to more generation of interface states due to an increase in the high-energy tail electrons. By the theory of electron-electron scattering, the threshold voltage shift was the most severe at the condition of VG&amp;gt;VD. However, based on the results of extrapolating the device lifetime, the worst case stress condition under HCS was the VG=VD condition at elevated temperature due to a higher generation rate.

Worst case stress conditions for hot carrier induced degradation of p-channel SOI MOSFETs

In this paper a comprehensive study of the worst case hot carrier stress conditions for p-channel partially depleted SOI MOSFETs is carried out. It is found that while stress at maximum gate current results to the conventional PMOSFET degradation mechanism (i.e., electron trapping in the gate oxide on the drain side), significant damage is also introduced following stress at the high gate/high drain voltage ( V G = V D) condition. A series of experiments unambiguously demonstrate that this damage is not caused by hot hole injection and that device degradation mechanism at V G = V D stress condition (formation of interface states and positive oxide charges) is in fact due to negative bias temperature instability which is activated because of the self-heating effect. In addition, stress at high temperature is found to result in a shift of the worst case stress condition from maximum gate current to V G = V D.

Examination of the Stress Distribution in the Tip of a Pencil

The stresses within the tip of a pencil are examined theoretically, numerically, and experimentally to determine the position and orientation of the fracture surface. The von Mises stress is used to evaluate the impact of the normal and shear stresses due to compression, bending, torsion, and shear. The worst-case stress is shown to occur along the top edge of the inclined pencil point, where the normal stress is compressive. The resulting crack propagates diagonally downwards and towards the tip from this initial position, and is frequently observed to contain a cusp.

Empirical reliability modeling for 0.18-μm MOS devices

This paper presents a simple yet effective approach to modeling empirically the 0.18-μm MOS reliability. Short-term stress data are first measured, and the well-known power law is used to project the MOS long-term degradation and lifetime. These results are then used as the basis for the development of an empirical model to predict the MOS lifetime as a function of drain voltage and channel length. Our study focuses on the worst-case stress condition, and both the linear and saturation operations are considered in the modeling. Very good agreement between the measurements and model calculations has been demonstrated.

B 2 and C2 Stress Indices for Large-Angle Bends

B 2 and C2 stress indices are needed for evaluation of nuclear piping components. These indices are used in calculation of stress terms corresponding to moment loading. The formulas (B2=1.3/h2/3 and C2=1.95/h2/3) given in the ASME Boiler and Pressure Vessel Code for calculating these stress indices for elbows and bends are independent of bend angle. Author’s earlier work indicated that the values obtained by these formulas are conservative for bend angle ⩽90 deg. The objective of the present study was to investigate the values of B2 and C2 stress indices for elbows with bend angles larger than 90 deg and to evaluate the limit of the applicability of the ASME Code formulas in terms of the bend angle. For this purpose, elbows with bend angles ranging from 90 to 180 deg have been investigated in detail. Elbow sizes studied ranged from 2.5 to 20 NPS. Finite element models have been used for detailed analysis. To cover the worst case of stresses in the elbows, several hundred load cases were analyzed by varying the direction of the moment loading. It was found that the three independent loading cases corresponding to three orthogonal axes do not bound the worst-case stress in the elbows. The results of the analysis show that the calculated value of B2 stress index increases with bend angle; but its value, even for 180-deg bend angle, remains below the ASME Code value with a margin of at least 15%. Considering all analyzed elbows and bend angles from 90 to 180 deg, the calculated maximum value of C2 stress index is found to be within 2 percent of the ASME Code value. The maximum increase in the value of B2 stress index is 12.5 percent as the bend angle is increased from 90 to 180 deg. The corresponding increase in the C2 stress index is less than 8%. Based on these results and authors’ earlier work, a modification to ASME Code formulas is proposed for calculation of more realistic values of the stress indices for bends up to 180 deg.

Low and high temperature device reliability investigations of buried p-channel MOSFETs of a 0.17 μm technology

The hot carrier degradation of buried p-channel MOSFETs of a 0.17 μm technology is assessed in the temperature range between −40°C and 125°C. Within this temperature range, the degradation of the electrical parameter is investigated for different drain voltages and channel lengths (0.2–0.3 μm) in the gate voltage range between V GS=0 V and V GS= V DS. The analysis of the experimental results is presented and the physical processes responsible for the observed degradation at different stress conditions are discussed by reviewing previous works. Based on hot carrier modelling and lifetime extrapolation to operating conditions the stressing voltage conditions are analysed. For the experimentally investigated temperature range the worst case stress condition is identified at low temperatures for gate voltage at the maximum of the gate current ( I G max ). In the case of V GS corresponding to I G max two activation energies are determined for low and high temperatures. For temperatures above 125°C the worst case bias condition changes from V GS =V GS @I G max to V GS= V DS.

Influence of the lightly doped drain resistance on the worst-case hot-carrier stress condition for NMOS devices

In this paper the underlying mechanisms that produce the cross-over in worst-case hot-carrier stress condition observed at room temperature in some deep submicron lightly doped drain (LDD) NMOS devices and at cryogenic temperatures for devices with longer channel lengths are investigated. Experiments were performed that demonstrate the generality of the cross-over. The role of stress temperature, measurement temperature and stress condition were experimentally addressed. The temperature dependence of the mobility was measured, and an analysis is presented that shows that mobility changes alone do not explain the observed changes in the transconductance. A model is proposed that allows for changes in the source–drain resistance with stress time. It is suggested that the origin of the time-dependent increasing source–drain resistance is the injection of charge, either in the form of fixed charge or as interface states, into the spacer oxide above the LDD region. This model is used to explain the qualitative dependence of the worst-case stress condition on channel length and temperature. Finally, it is suggested that the methodology used to design the LDD structure be modified to account for these new observations.

Projecting lifetime of deep submicron MOSFETs

A detailed examination of hot-carrier-induced degradation in MOSFETs from a 0.25-/spl mu/m and a 0.1-/spl mu/m technology is performed. Although the worst case stress condition depends on the stress voltage, channel length, and oxide thickness, I/sub b,peak/ is projected to be the worst case stress condition at the operating voltage for both nMOSFETs and pMOSFETs. Post-metallization anneal (PMA) in deuterium can significantly improve the device lifetime if the primary degradation mechanism at the stress condition is interface trap generation due to interface depassivation by energetic electrons.

Theoretical assessment of bulk current injection versus radiation

Field excitation and bulk current injection (BCI) on a wire bundle are analytically compared. The equivalence of the two excitation techniques is investigated in order to ascertain the validity of using current injection testing rather than radiated immunity testing for an equipment connected at one end of the bundle. The wire bundle is modeled as a multiconductor transmission line which, throughout the analysis, is treated as a multiport device. The equivalence is discussed by comparing the effects that the sources produce at the terminal ports, with the aim to control the clamp voltage in order to match the incident field characteristics. This approach yields general results, which are not affected by any assumptions on the terminal networks. It is shown that one injection probe is not sufficient to assure the equivalence in the general case, but it is possible, although practically difficult, to achieve this result by employing two injection probes. In the simpler but more specific case of linear terminations, a test procedure is proposed which allows equivalence by using a single injection current probe. Since the ideal BCI procedure must represent a worst-case stress analysis for the equipment under test, the possibility of adopting BCI tests to reproduce the upper envelope of the radiation-induced currents is also investigated. In this case practical difficulties are evidenced and arise from the need of feeding the injection probes with a complicated frequency-dependent power distribution.