Worst-case Response Time Research Articles

Controller area network with priority queues and FIFO queues: improved schedulability analysis and message set extension

Controller area network (CAN) enables communication of electronic control units (ECUs) via messages using priority-based arbitration, which requires the implementation of priority queues (PQs) in the ECU device driver. Nevertheless, it is possible that not all ECUs on a CAN support PQs but use FIFO queues (FQs) instead. In this case, the classical CAN scheduling model with PQs is not suitable for the computation of message worst-case response times (WCRTs) that are essential for verifying the correct vehicle operation. This paper considers an existing scheduling model for CAN with both PQs and FQs. First, an improved algorithm for speeding up the WCRT computation is proposed. Second, the practical case where an existing CAN message set is extended by new messages is addressed. An original algorithm for assigning priorities to new messages while keeping the priority order of existing messages is developed. Both algorithms are evaluated by computational experiments.

Improved Automotive CAN Protocol Based on Payload Reduction and Selective Bit Stuffing

In this research paper, the implementation strategies of automotive controller area network protocol are investigated and the short messaging scheme with selective bit stuffing method to improve the effective utilization of its bandwidth has been proposed. There would be a sharp decrease in the performance of traditional CAN protocol because of considerable increase in the number of ECUs (Electronic Control Units) and infotainment gadgets connected in the vehicle architecture. The demand for safety, emission, diagnostics and comfort norms has steeply increased the number of messages in the 250 Kbps CAN network as the computational power of ECUs has gone up. To overcome this problem, the short CAN method has been proposed and the work is benchmarked with SAEJ1939 Heavy commercial vehicle CAN standard. The Matlab Simulink based short CAN has been modeled and the performance of the proposed system has evaluated using virtual instrument cluster. Experimental results have shown that compared to the traditional CAN, the proposed method has reduced the worst case response time of CAN extended frame from 160 μ sec to 144 μ sec. Selective bit stuffing technique has reduced the impact of bit stuffing over the payload and improved the utilization factor for the CAN bus without affecting the CAN message ID properties. The proposed algorithm has been modeled and simulated using CAN Matlab model Simulink and it has been verified using virtual CAN tool and real time CAN bus hardware.

Computational Cost Reduction for Real-Time Schedulability Tests Algorithms

This paper focuses on reducing the computational cost of iterative algorithms used to evaluate the schedulability of Real-Time Systems. These algorithms calculate the worst case response time of each task. Through simulations it is found that the proposed new algorithm produces a significant reduction in the average temporal cost, reaching in some cases a reduction of O(n2) to O(n.log(n)), with respect to classical response time evaluation algorithms.

Symbolic execution and timed automata model checking for timing analysis of Java real-time systems

This paper presents SymRT, a tool based on a combination of symbolic execution and real-time model checking for timing analysis of Java systems. Symbolic execution is used for the generation of a safe and tight timing model of the analyzed system capturing the feasible execution paths. The model is combined with suitable execution environment models capturing the timing behavior of the target host platform including the Java virtual machine and complex hardware features such as caching. The complete timing model is a network of timed automata which directly facilitates safe estimates of worst and best case execution time to be determined using the Uppaal model checker. Furthermore, the integration of the proposed techniques into the TetaSARTS tool facilitates reasoning about additional timing properties such as the schedulability of periodically and sporadically released Java real-time tasks (under specific scheduling policies), worst case response time, and more.

Response time analysis for fixed priority real-time systems with energy-harvesting

This paper introduces sufficient schedulability tests for fixed-priority pre-emptive scheduling of a real-time system under energy constraints. In this problem, energy is harvested from the ambient environment and used to replenish a storage unit or battery. The set of real-time tasks is decomposed into two different types of task depending on whether their rate of energy consumption is (i) more than or (ii) no more than the storage unit replenishment rate. We show that for this task model, where execution may only take place when there is sufficient energy available, the worst-case scenario does not necessarily correspond to the synchronous release of all tasks. We derive sufficient schedulability tests based on the computation of worst-case response time upper and lower bounds. We show that these tests are sustainable with respect to decreases in the energy consumption of tasks, and increases in the storage unit replenishment rate. Further, we show that Deadline Monotonic priority assignment is optimal with respect to the derived tests. We examine both the effectiveness and the tightness of the bounds, via an empirical investigation.

Architecture and analysis of a dynamically-scheduled real-time memory controller

Memory controller design is challenging as mixed time-criticality embedded systems feature an increasing diversity of real-time (RT) and non-real-time (NRT) applications with variable transaction sizes. To satisfy the requirements of the applications, tight bounds on the worst-case response time (WCRT) of memory transactions must be provided to RT applications, while the lowest possible average response time must be given to the remaining applications. Existing real-time memory controllers cannot efficiently achieve this goal as they either bound the WCRT by sacrificing the average response time, or cannot efficiently support variable transaction sizes. In this article, we propose to use dynamic command scheduling, which is capable of efficiently dealing with transactions with variable sizes. The three main contributions of this article are: (1) a memory controller architecture consisting of a front-end and a back-end, where the former uses a TDM arbiter with a new work-conserving policy and the latter has a dynamic command scheduling algorithm that is independent of the front-end, (2) a formalization of the timings of the memory transactions for the proposed algorithm and architecture, and (3) an analysis of WCRT for transactions to capture the behavior of both the front-end and the back-end. This WCRT analysis supports variable transaction sizes and different degrees of bank parallelism. The critical part of the WCRT is the worst-case execution time (WCET) of a transaction, which is the time spent on command scheduling in the back-end. The WCET is bounded by two techniques applied to both fixed and variable transaction sizes, respectively. We experimentally evaluate the proposed memory controller and compare to an existing semi-static approach. The results demonstrate that dynamic command scheduling significantly outperforms the semi-static approach in the average case, while it performs equally well or better in the worst-case with only a few exceptions. The former reduces the average response time for NRT applications, and the latter pertains the WCRT for RT applications.

An <sc>fptas</sc> for Response Time Analysis of Fixed Priority Real-Time Tasks with Resource Augmentation

Response time analysis is required both for on-line admission of applications in dynamic systems and as an integral part of design tools for complex distributed real-time systems. We consider sporadic tasks with fixed-priorities and arbitrary deadlines to be executed upon a uniprocessor platform. Pseudo-polynomial time algorithms are known for computing exact worst-case response times for this task model. Nevertheless, the problem is known NP-hard and there cannot exist a constant approximation algorithm for response time computation, unless P=NP. We propose a fully polynomial time approximation scheme (FPTAS) for computing response time upper bounds under resource augmentation. The resource augmentation is defined as the processor speedup factor bounded by (1 + 1/k), where k <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">def</sup> [1 = ε]-1 for any constant ε ∈ (0;1), the FPTAS accuracy parameter. This algorithm is best possible in the sense that resource augmentation is indeed necessary for an efficient response time calculation.

Mixed-criticality scheduling on cluster-based manycores with shared communication and storage resources

The embedded system industry is facing an increasing pressure for migrating from single-core to multi- and many-core platforms for size, performance and cost purposes. Real-time embedded system design follows this trend by integrating multiple applications with different safety criticality levels into a common platform. Scheduling mixed-criticality applications on today's multi/many-core platforms and providing safe worst-case response time bounds for the real-time applications is challenging given the shared platform resources. For instance, sharing of memory buses introduces delays due to contention, which are non-negligible. Bounding these delays is not trivial, as one needs to model all possible interference scenarios. In this work, we introduce a combined analysis of computing, memory and communication scheduling in a mixed-criticality setting. In particular, we propose: (1) a mixed-criticality scheduling policy for cluster-based many-core systems with two shared resource classes, i.e., a shared multi-bank memory within each cluster, and a network-on-chip for inter-cluster communication and access to external memories; (2) a response time analysis for the proposed scheduling policy, which takes into account the interferences from the two classes of shared resources; and (3) a design exploration framework and algorithms for optimizing the resource utilizations under mixed-criticality timing constraints. The considered cluster-based architecture model describes closely state-of-the-art many-core platforms, such as the Kalray MPPA®-256. The applicability of the approach is demonstrated with a real-world avionics application. Also, the scheduling policy is compared against state-of-the-art scheduling policies based on extensive simulations with synthetic task sets.

Heterogeneity-driven end-to-end synchronized scheduling for precedence constrained tasks and messages on networked embedded systems

Scheduling for a directed acyclic graph (DAG) on networked embedded systems is to maximize concurrency and minimize inter-processor communication for minimum end-to-end worst-case response time (WCRT). Time accuracy and synchronization are critical for scheduling on heterogeneous networked embedded systems, where computing and networking are both heterogeneous and deeply jointed. Most algorithms use the upward rank value for task prioritization, and the earliest finish time for processor selection. In order to obtain accurate and efficient schedules in heterogeneous networked systems, the above approaches can be improved. Moreover, synchronization with tasks and messages is critical for end-to-end WCRT. However, task scheduling and message scheduling are isolated in most approaches in communication contention environments. In this paper, a heterogeneity-driven task scheduling algorithm called Heterogeneous Selection Value (HSV) based on the classic model, and a heterogeneity-driven end-to-end synchronized scheduling algorithm called Heterogeneous Selection Value on Communication Contention (HSV_CC) based on the communication contention model are proposed to address the above problems. Both benchmark and extensive experimental evaluation demonstrate significant performance improvement of the proposed algorithms.

Schedulability of Fault Tolerant Real Time System Based on Local Optimum Checkpoint Under Priority Mixed Strategy

Against the defect of the real time system fault tolerant model that can only tolerate one fault, the Local optimum checkpoint (LOC) algorithm was proposed. Then according to the schedulability analysis, the worst case response time formula under the fault tolerant priority mixed strategy based on the local optimum checkpoint was deduced. Finally the Fault tolerant priority configuration search algorithm under Mixed strategy based on LOC (FTPCS-MS-LOC) was proposed. The FTPCS-MS-LOC can toleratemultiple transient faults. The algorithm can effectively reduce the search space compared to the enumeration method. The simulation shows that the FTPCS-MSLOC can significantly improve the system fault resilience than the fault tolerant priority inheritance, promotion and demotion strategy, and also the mixed strategy based on the checkpoint interval in the condition of single fault occurred.

Worst Case Response Time Analysis of Sporadic Traffic in MVB

The Multifunction Vehicle Bus (MVB) protocol is well applied to train network control system where a set of process variables must be transferred between network devices. To cope with the real-time requirements of such system, the MVB protocol is designed to support both periodic and sporadic traffic. The periodic traffic is handled according to a static scheduling table, thus the schedulability can be certain after system initialization. However, for the sporadic traffic, the situation is different due to their irregular occurrence in the system. Therefore, more complex analysis must be made in order to guarantee its timing requirements. In this paper, a schedulability analysis is made by executing worst case response time analysis for sporadic traffic in MVB network.

A Technique to Calculate Cache Related Preemption Delay Using Constraints on Non-nested Preemptions

Abstract Caches incur an indirect cost to the response times of tasks due to preemptions in a task system. Hence the computation of Cache Related Preemption Delay (CRPD) is an important problem to assess the schedulability of a task system. In this paper, we have introduced the concept of inhibiting and non-nested preemptions. We have proposed a novel method to calculate tight upper and lower bounds on the number of preemptions of every task in the task-system across all phases . The problem of calculation of CRPD is modelled as a constraint satisfaction problem that can be solved by using Integer Linear Programming (ILP). The CRPD values are integrated in the worst case response time analysis.

Improved Blocking Time Analysis and Evaluation for the Multiprocessor Priority Ceiling Protocol

The Multiprocessor Priority Ceiling Protocol (MPCP) is a classic suspension-based real-time locking protocol for partitioned fixed-priority (P-FP) scheduling. However, existing blocking time analysis is pessimistic under the P-FP + MPCP scheduling, which negatively impacts the schedulability for real-time tasks. In this paper, we model each task as an alternating sequence of normal and critical sections, and use both the best-case execution time (BCET) and the worst-case execution time (WCET) to describe the execution requirement for each section. Based on this model, a novel analysis is proposed to bound shared resource requests. This analysis uses BCET to derive the lower bound on the inter-arrival time for shared resource requests, and uses WCET to obtain the upper bound on the execution time of a task on critical sections during an arbitrary time interval of Δt. Based on this analysis, improved blocking analysis and its associated worst-case response time (WCRT) analysis are proposed for P-FP + MPCP scheduling. Schedulability experiments indicate that the proposed method outperforms the existing methods and improves the schedulability significantly.

A formal approach to the WCRT analysis of multicore systems with memory contention under phase-structured task sets

Multicore technology has the potential for drastically increasing productivity of embedded real-time computing. However, joint use of hardware, e.g., caches, memory banks and on-chip buses makes the integration of multiple real-time applications into a single system difficult: resource accesses are exclusive and need to be sequenced. Moreover, resource access schemes of modern off-the-shelf multicore chips are commonly optimized for the average-case, rather than being timing predictable. Real-time analysis for such architectures is complex, as execution times depend on the deployed hardware, as well as on the software executing on other cores. This will ask for significant abstractions in the timing analysis, where the resulting pessimism will lead to over-provisioned system designs and a lowered productivity as the number of applications to be put together into a single architecture needs to be decreased. In response to this, (a) we present a formal approach for bounding the worst-case response time of concurrently executing real-time tasks under resource contention and almost arbitrarily complex resource arbitration policies, with a focus on main memory as shared resource, (b) we present a simulation framework which allows for detailed modeling and empirical evaluation of modern multicore platforms and applications running on top of them, and (c) we present experiments to demonstrate the advantages and disadvantages of the presented methodologies and compare their accuracy. For limiting non-determinism inherent to the occurrence of cache misses, we particularly take advantage from the predictable execution model as discussed in recent works.

Integrating mixed transmission and practical limitations with the worst-case response-time analysis for Controller Area Network

The existing worst-case response-time analysis for Controller Area Network (CAN) calculates upper bounds on the response times of messages that are queued for transmission either periodically or sporadically. However, it does not support the analysis of mixed messages. These messages do not exhibit a periodic activation pattern and can be queued for transmission both periodically and sporadically. They are implemented by several higher-level protocols based on CAN that are used in the automotive industry. We extend the existing analysis to support worst-case response-time calculations for periodic and sporadic as well as mixed messages. Moreover, we integrate the effect of hardware and software limitations in the CAN controllers and device drivers such as abortable and non-abortable transmit buffers with the extended analysis. The extended analysis is applicable to any higher-level protocol for CAN that uses periodic, sporadic and mixed transmission modes.

Precautious-RM: a predictable non-preemptive scheduling algorithm for harmonic tasks

A major requirement of many real-time embedded systems is to have time-predictable interaction with the environment. More specifically, they need fixed or small sampling and I/O delays, and they cannot cope with large delay jitters. Non-preemptive execution is a known method to reduce the latter delay; however, the corresponding scheduling problem is NP-Hard for periodic tasks. In this paper, we present Precautious-RM as a predictable linear-time online non-preemptive scheduling algorithm for harmonic tasks which can also deal with the former delay, namely sampling delay. We derive conditions of optimality of Precautious-RM and show that satisfying those conditions, tight bounds for best- and worst-case response times of the tasks can be calculated in polynomial-time. More importantly, response time jitter of the tasks is analyzed and it is proven that under specific conditions, each task has either one or two values for response time, which leads to improving the predictability of the system interaction with the environment. Simulation results demonstrate efficiency of Precautious-RM in increasing accuracy of control applications.

Marcapasos transitorio a través de bolsa pericárdica

The existing worst-case response-time analysis for Controller Area Network (CAN) calculates upper bounds on the response times of messages that are queued for transmission either periodically or sporadically. However, it does not support the analysis of mixed messages. These messages do not exhibit a periodic activation pattern and can be queued for transmission both periodically and sporadically. They are implemented by several higher-level protocols based on CAN that are used in the automotive industry. We extend the existing analysis to support worst-case response-time calculations for periodic and sporadic as well as mixed messages. Moreover, we integrate the effect of hardware and software limitations in the CAN controllers and device drivers such as abortable and non-abortable transmit buffers with the extended analysis. The extended analysis is applicable to any higher-level protocol for CAN that uses periodic, sporadic and mixed transmission modes.

Cache-related preemption delay analysis for FIFO caches

Hard real-time systems are typically composed of multiple tasks, subjected to timing constraints. To guarantee that these constraints will be respected, the Worst-Case Response Time (WCRT) of each task is needed. In the presence of systems supporting preemptible tasks, we need to take into account the time lost due to task preemption. A major part of this delay is the Cache-Related Preemption Delay (CRPD), which represents the penalties due to cache block evictions by preempting tasks. Previous works on CRPD have focused on caches with Least Recently used (LRU) replacement policy. However, for many real-world processors such as ARM9 or ARM11, the use of First-in-first-out (FIFO) cache replacement policy is common. In this paper, we propose an approach to compute CRPD in the presence of instruction caches with FIFO replacement policy. We use the result of a FIFO instruction cache categorization analysis to account for single-task cache misses, and we model as an Integer Linear Programming (ILP) system the additional preemption-related cache misses. We study the effect of cache related timing anomalies, our work is the first to deal with the effect of timing anomalies in CRPD computation. We also present a WCRT computation method that takes advantage of the fact that our computed CRPD does not increase linearly with respect to the preemption count. We evaluated our method by computing the CRPD with realistic benchmarks (e.g. drone control application, robot controller application), under various cache configuration parameters. The experimentation shows that our method is able to compute tight CRPD bound for benchmark tasks.

An Efficient Test Method for Rate Monotonic Schedulability

Rate Monotonic scheduling algorithm has been widely used in real-time systems for its optimality in fixed priority scheduling. Determining the Rate Monotonic schedulability of tasks is an important problem when designing a real-time system. There are exact schedulability test methods for Rate Monotonic scheduling, but the worst case response time analysis on which the exact tests are based is NP-hard. So the exact tests are often too complex to be executed on-line for large numbers of tasks. For practical use, polynomial time sufficient conditions for the Rate Monotonic schedulability have been studied. However, existing polynomial time tests are often too pessimistic. In this paper, we propose a new polynomial time sufficient condition based on the response time analysis, which is less pessimistic than existing ones. Simulation results show that our test significantly outperforms the existing tests and has performance close to the exact test.

Computation of the Precise Worst-Case Response Time of FlexRay Dynamic Messages

FlexRay is a communication bus (and associated protocol) that supports transmission of time-triggered and event-triggered frames. A method for determining the worst-case response-time of FlexRay frames is proposed by Pop in 2008, and is formulated as iterative sequence of Integer Linear Programming (ILP) problems. As we show, the method of Pop is conservative (overestimates the response time). We propose a new ILP formulation that computes a precise value of the worst-case response time of FlexRay frames transmitted in the dynamic segment. Furthermore, our approach is non-iterative as it requires the solving of a single ILP for computing, respectively, the delay of full bus cycles and the delay of a partial (last) bus cycle. The proposed solution is also validated by applying it to a SAE benchmark and can be used for formally guaranteeing that no message will miss its deadline during system operation.