Worst-case Execution Time Estimates Research Articles

Worst Case Execution Time and Power Estimation of Multicore and GPU Software: A Pedestrian Detection Use Case

Worst Case Execution Time estimation of software running on parallel platforms is a challenging task, due to resource interference of other tasks and the complexity of the underlying CPU and GPU hardware architectures. Similarly, the increased complexity of the hardware, challenges the estimation of worst case power consumption. In this paper, we employ Measurement Based Probabilistic Timing Analysis (MBPTA), which is capable of managing complex architectures such as multicores. We enable its use by software randomisation, which we show for the first time that is also possible on GPUs. We demonstrate our method on a pedestrian detection use case on an embedded multicore and GPU platform for the automotive domain, the NVIDIA Xavier. Moreover, we extend our measurement based probabilistic method in order to predict the worst case power consumption of the software on the same platform.

Mitigating Mode-switch through Run-time Computation of Response Time

Mixed-critical systems consist of applications with different criticality. In these systems, different confidence levels of Worst-Case Execution Time (WCET) estimations are used. Dual criticality systems use a less pessimistic, but with lower level of assurance, WCET estimation, and a safe, but pessimistic, WCET estimation. Initially, both high and low criticality tasks are executed. When a high criticality task exceeds its less pessimistic WCET, the system switches mode and low criticality tasks are usually dropped, reducing the overall system Quality of Service (QoS). To postpone mode switch, and thus, improve QoS, existing approaches explore the slack, created dynamically, when the actual execution of a task is faster than its WCET. However, existing approaches observe this slack only after the task has finished execution. To enhance dynamic slack exploitation, we propose a fine-grained approach that is able to expose the slack during the progress of a task, and safely uses it to postpone mode switch. The evaluation results show that the proposed approach has lower cost and achieves significant improvements in avoiding mode-switch, compared to existing approaches.

Predictable GPU Wavefront Splitting for Safety-Critical Systems

We present a predictable wavefront splitting (PWS) technique for graphics processing units (GPUs). PWS improves the performance of GPU applications by reducing the impact of branch divergence while ensuring that worst-case execution time (WCET) estimates can be computed. This makes PWS an appropriate technique to use in safety-critical applications, such as autonomous driving systems, avionics, and space, that require strict temporal guarantees. In developing PWS on an AMD-based GPU, we propose microarchitectural enhancements to the GPU, and a compiler pass that eliminates branch serializations to reduce the WCET of a wavefront. Our analysis of PWS exhibits a performance improvement of 11% over existing architectures with a lower WCET than prior works in wavefront splitting.

Estimating Probabilistic Safe WCET Ranges of Real-Time Systems at Design Stages

Estimating worst-case execution time (WCET) is an important activity at early design stages of real-time systems. Based on WCET estimates, engineers make design and implementation decisions to ensure that task executions always complete before their specified deadlines. However, in practice, engineers often cannot provide precise point WCET estimates and prefer to provide plausible WCET ranges. Given a set of real-time tasks with such ranges, we provide an automated technique to determine for what WCET values the system is likely to meet its deadlines and, hence, operate safely with a probabilistic guarantee. Our approach combines a search algorithm for generating worst-case scheduling scenarios with polynomial logistic regression for inferring probabilistic safe WCET ranges. We evaluated our approach by applying it to three industrial systems from different domains and several synthetic systems. Our approach efficiently and accurately estimates probabilistic safe WCET ranges within which deadlines are likely to be satisfied with a high degree of confidence.

Analysis of benchmark program results of worst case execution time for multithreaded programs

<span lang="EN-US">Worst case execution time (WCET) estimation by static analyzers is being investigated with keen interest in view of their importance in designing applications for embedded systems that have real- time requirements. Recent work reported on improving precision of estimates of WCET of multithreaded programs, by improving precision of shared instruction cache analysis, shows significant improvement in WCET estimates. An abstraction of a multithreaded program as Hoare’s communicating sequential processes (CSP) specification program is realized to enable higher precision in micro-architectural modelling unit of WCET analyzer of multithreaded programs. A thread is viewed as a composition of CSP. The WCET of a thread may be viewed as dependent on WCET of processes in a thread and in turn WCET of each process is the WCET of the sub-graph of basic block nodes in the process. Corresponding CSP in interacting threads, based on calls to synchronization primitives wait and notify, generate shared cache interferences to the process in a thread whose WCET is being estimated by the analyzer. A detailed study of how partitioning of a thread into processes yields higher reduction in WCET is performed on benchmark programs. Furthermore, which processes in a thread yield higher reduction in WCET is performed.</span>

A generic framework to integrate data caches in the WCET analysis of real-time systems

Worst-case execution time (WCET) analysis of systems with data caches is one of the key challenges in real-time systems. Caches exploit the inherent reuse properties of programs by temporarily storing certain memory contents near the processor, in order that further accesses to such contents do not require costly memory transfers. Current worst-case data cache analysis methods focus on specific cache organizations (set-associative LRU, locked, ACDC, etc.), most of the times adapting techniques designed to analyze instruction caches. On the other hand, there are methodologies to analyze the data reuse of a program, independently of the data cache. In this paper we propose a generic WCET analysis framework to analyze data caches taking profit of such reuse information. It includes the categorization of data references and their integration in an IPET model. We apply it to a conventional LRU cache, an ACDC, and other baseline systems, and compare them using the TACLeBench benchmark suite. Our results show that persistence-based LRU analyses dismiss essential information on data, and a reuse-based analysis improves the WCET bound around 17% in average. In general, the best WCET estimations are obtained with optimization level 2, where the ACDC cache performs 39% better than a set-associative LRU.

Schedulability of probabilistic mixed-criticality systems

Mixed-criticality systems often need to fulfill safety standards that dictate different requirements for each criticality level, for example given in the ‘probability of failure per hour’ format. A recent trend suggests designing this kind of systems by jointly scheduling tasks of different criticality levels on a shared platform. When this is done, the usual assumption is that tasks of lower criticality are degraded when a higher criticality task needs more resources, for example when it overruns a bound on its execution time. However, a way to quantify the impact this degradation has on the overall system is not well understood. Meanwhile, to improve schedulability and to avoid over-provisioning of resources due to overly pessimistic worst-case execution time estimates of higher criticality tasks, a new paradigm emerged where task’s execution times are modeled with random variables. In this paper, we analyze a system with probabilistic execution times, and propose metrics that are inspired by safety standards. Among these metrics are the probability of deadline miss per hour, the expected time before degradation happens, and the duration of the degradation. We argue that these quantities provide a holistic view of the system’s operation and schedulability.

Mixed-Criticality Scheduling Upon Permitted Failure Probability and Dynamic Priority

Many safety-critical real-time systems are considered certified when they meet failure probability requirements with respect to the maximum permitted incidences of failure per hour. In this article, the mixed-criticality task model with multiple worst case execution time (WCET) estimations is extended to incorporate such system-level certification restrictions. A new parameter is added to each task, characterizing the distribution of WCET estimations—the likelihood of all jobs of a task finishing their executions within the less pessimistic WCET estimates. Efficient algorithms are derived for scheduling mixed-criticality systems represented using this model for both uniprocessor and multiprocessor platforms for independent tasks. Furthermore, a 0/1 covariance matrix is introduced to represent the failure dependency between tasks. An efficient algorithm is proposed to schedule such failure-dependent tasks. Experimental analyses show our new model and algorithm outperform current state-of-the-art mixed-criticality scheduling algorithms.

Response time analysis of multiframe mixed-criticality systems with arbitrary deadlines

The well-known model of Vestal aims to avoid excessive pessimism in the quantification of the processing requirements of mixed-criticality systems, while still guaranteeing the timeliness of higher-criticality functions. This can bring important savings in system costs, and indirectly help meet size, weight and power constraints. This efficiency is promoted via the use of multiple worst-case execution time (WCET) estimates for the same task, with each such estimate characterized by a confidence associated with a different criticality level. However, even this approach can be very pessimistic when the WCET of successive instances of the same task can vary greatly according to a known pattern, as in MP3 and MPEG codecs or the processing of ADVB video streams. In this paper, we present a schedulability analysis for the new multiframe mixed-criticality model, which allows tasks to have multiple, periodically repeating, WCETs in the same mode of operation. Our work extends both the analysis techniques for Static Mixed-Criticality scheduling (SMC) and Adaptive Mixed-Criticality scheduling (AMC), on one hand, and the schedulability analysis for multiframe task systems on the other. A constrained-deadline model is initially targeted, and then extended to the more general, but also more complex, arbitrary-deadline scenario. The corresponding optimal priority assignment for our schedulability analysis is also identified. Our proposed worst-case response time (WCRT) analysis for multiframe mixed-criticality systems is considerably less pessimistic than applying the static and adaptive mixed-criticality scheduling tests oblivious to the WCET variation patterns. Experimental evaluation with synthetic task sets demonstrates up to 20% and 31.4% higher scheduling success ratio (in absolute terms) for constrained-deadline analyses and arbitrary-deadline analyses, respectively, when compared to the best of their corresponding frame-oblivious tests.

Dynamic Memory Bandwidth Allocation for Real-Time GPU-Based SoC Platforms

Heterogeneous SoC platforms, comprising both general purpose CPUs and accelerators, such as a GPU, are becoming increasingly attractive for real-time and mixed-criticality systems to cope with the computational demand of data parallel applications. However, contention for access to shared main memory can lead to significant performance degradation on both CPU and GPU. Existing work has shown that memory bandwidth throttling is effective in protecting real-time applications from memory-intensive, best-effort (BE) ones; however, due to the inherent pessimism involved in worst-case execution time (WCET) estimation, such approaches can unduly restrict the bandwidth available to BE applications. In this article, we propose a novel memory bandwidth allocation scheme where we dynamically monitor the progress of a real-time application and increase the bandwidth share of BE ones whenever it is safe to do so. Specifically, we demonstrate our approach by protecting a real-time GPU kernel from BE CPU tasks. Based on profiling information, we first build a WCET estimation model for the GPU kernel. Using such model, we then show how to dynamically recompute on-line the maximum memory budget that can be allocated to BE tasks without exceeding the kernel’s assigned execution budget. We implement our proposed technique on NVIDIA embedded SoC and demonstrate its effectiveness on a variety of GPU and CPU benchmarks.

Dealing with Uncertainty in pWCET Estimations

The problem of estimating a tight and safe Worst-Case Execution Time (WCET), needed for certification in safety-critical environment, is a challenging problem for modern embedded systems. A possible solution proposed in past years is to exploit statistical tools to obtain a probability distribution of the WCET. These probabilistic real-time analyses for WCET are, however, subject to errors, even when all the applicability hypotheses are satisfied and verified. This is caused by the uncertainties of the probabilistic-WCET distribution estimator. This article aims at improving the measurement-based probabilistic timing analysis approach providing some techniques to analyze and deal with such uncertainties. The so-called region of acceptance model based on state-of-the-art statistical test procedures is defined over the distribution space parameters. From this model, a set of strategies is derived and discussed to provide the methodology to deal with the trade-off safety/tightness of the WCET estimation. These techniques are then tested over real datasets, including industrial safety-critical applications, to show the increased value of using the proposed approach in probabilistic WCET analyses.

EMSBench: Benchmark and Testbed for Reactive Real-Time Systems

Benchmark suites for real-time embedded systems (RTES) usually contain only pure computations that are often used in this domain. They allow to evaluate computing performance, but do not reproduce the complexity and behaviour that is typical for such systems. Actual RTES have to interact with the physical environment, which is often reflected by code that is executed concurrently. In this article, we present the software package EMSBench that mimics such complex behaviour, and highlight some of its use cases. The benchmark code ems of EMSBench is based on the open-source engine management system (EMS) FreeEMS. Additionally, EMSBench contains a trace generator (tg) that provides input signals for ems and enables to execute ems close to reality. We provide detailed descriptions of the ems's execution behaviour and of trace generation. EMSBench can be used as test or benchmark program to compare different hardware platforms, e.g. in terms of schedulability. Also, we use EMSBench as a benchmark for static worst-case execution time (WCET) analysis and compare these results to measurements performed on existing hardware. Our results based on the OTAWA WCET estimation tool show WCET overestimations by the static analysis from 11.9% to 41.1% depending on the complexity of the analysed functions.

Fast and Predictable Non-Volatile Data Memory for Real-Time Embedded Systems

Energy consumption and predictability are two important constraints in designing real-time embedded systems and one of the recently proposed solutions for the energy consumption problem is the use of non-volatile memories instead of conventional SRAM due to their lower leakage power consumption and smaller cell area. Furthermore, because of their non-volatile nature, the use of these memories helps normally-off computing and energy harvesting systems to resume their execution without a large startup delay. However, the write access latency of non-volatile memories is considerably more than that of SRAM which can decrease the performance and predictability of the system if not managed correctly. In this article, we present a predictable fully non-volatile data memory for real-time embedded systems which improves both worst-case execution time (WCET) and performance of the system using a hybrid hardware-software solution. As part of this solution, we add a special write buffer to the memory controller and adopt a multi-bank memory configuration which improves the overall latency of write operations. Since write buffers usually help with the performance problem but they make WCET estimation more complex, we also present a new low-overhead software-based optimization technique that makes the proposed system more predictable without imposing considerable overhead. Furthermore, we present the WCET analysis algorithm which can be used to estimate the WCET of applications during the design time. The results show that compared to a hybrid SRAM-NVM architecture, the proposed solution improves the WCET and performance by 33 and 47 percent, respectively.

A scenario- and platform-aware design flow for image-based control systems

Image-based control (IBC) systems are increasingly being used in various domains including autonomous driving. The key challenge in IBC is to deal with high computation demand while guaranteeing performance and safety requirements such as stability. While modern industrial heterogeneous platforms, such as NVIDIA Drive, offer the necessary compute power, application development on these platforms with performance and safety guarantees is still challenging. Alternative time-predictable platforms are not yet in widespread use.A typical design flow for IBC systems consists of three distinct elements: (i) mapping tasks onto platform resources; (ii) timing analysis, consisting of task-level worst-case execution time (WCET) analysis and application-level analysis to obtain worst-case performance bounds on aspects such as latency and throughput; (iii) controller design using the obtained performance bounds, ensuring performance and safety. While such a three-step design process is modular in nature, it usually leads to over-dimensioned systems with sub-optimal performance, because task- and/or application-level timing bounds are pessimistic.We present a scenario- and platform-aware design flow for IBC systems that exploits frequently occurring workload scenarios to optimize performance. For industrial platforms, where tight task-level WCET bounds are difficult to obtain, we moreover propose to use frequently occurring task execution times instead of WCET estimates to obtain tight application-level temporal bounds. During controller design, we then optimize performance and guarantee stability by identifying appropriate system scenarios and by designing a switched controller that switches between those scenarios. We illustrate our method considering a predictable multiprocessor system-on-chip platform - CompSOC. We validate the proposed method using hardware-in-the-loop (HiL) experiments with an industrial heterogeneous multiprocessor platform - NVIDIA Drive PX2 - considering a lane keeping assist system (LKAS). We obtain an improved control performance compared to state-of-the-art IBC design.

Execution Time of Optimal Controls in Hard Real Time, a Minimal Execution Time Solution for Nonlinear SDRE

Many engineering fields, such as automotive, aerospace, and the emerging challenges towards industry 4.0, have to deal with Real-Time (RT) or Hard Real Time (HRT) systems, where temporal constraints must be fulfilled, to avoid critical behaviours or unacceptable system failures. For this reason, estimation of code's Worst-Case Execution Time (WCET) has received lots attention because in RT systems a fundamental requirement is to guarantee at least a temporal upper bound of the code execution for avoiding any drawbacks. However, until now there is no approved method to compute extremely tight WCET. Nowadays, indeed, HRT requirements are solved via hardware, using multi-cores embedded boards that allow the computation of the deterministic Execution Time (ET). The availability of these embedded architectures has encouraged the designers to look towards more computationally demanding optimal control techniques for RT scenarios, and to compare and analyze performances also evaluating a tight WCET. However, this area still lacks deep investigations. This paper has the intent of analysing results regarding the choice between three of the most established optimal controls (LQR, MPC, SDRE), providing the first link between WCET analysis and control algorithms performances. Moreover, this work shows how it is also possible to obtain a minimal ET solution for the nonlinear SDRE controller. The results might be useful for future implementations and for coping with Industry 4.0 emerging challenges. Furthermore, this approach can be useful in control system engineering field, especially in the design stage for RT or HRT systems, where temporal bounds have to be fulfilled jointly with all the other application's specifications.

JMC: Jitter-Based Mixed-Criticality Scheduling for Distributed Real-Time Systems

These days, the term of Internet of Things (IoT) becomes popular to interact and cooperate with individual smart objects, and one of the most critical challenges for IoT is to achieve efficient resource sharing as well as ensure safety-stringent timing constraints. To design such reliable real-time IoT, this paper focuses on the concept of mixed-criticality (MC) introduced to address the low processor utilization on traditional real-time systems. Although different worst-case execution time estimates depending on criticality are proven effective on processor scheduling, the MC concept is not yet mature on distributed systems (such as IoT), especially with end-to-end deadline guarantee. To the best of our knowledge, this paper presents the first attempt to apply the MC concept into interference (or jitter), which is a complicated source of pessimism when analyzing the schedulability of distributed systems. Our goal is to guarantee the end-to-end deadlines of high-criticality flows and minimize the deadline miss ratio of low-criticality flows in distributed systems. To achieve this goal, we introduce a jitter-based MC (JMC) scheduling framework, which supports node-level mode changes in distributed systems. We present an optimal feasibility condition (subject to given schedulability analysis) and two policies to determine jitter-threshold values to achieve the goal in different conditions. Via simulation results for randomly generated workloads, JMC outperforms an existing criticality-monotonic scheme in terms of achieving higher schedulability and fewer deadline misses.

Determination of Worst-Case Data Using an Adaptive Surrogate Model for Real-Time System

The estimation of worst-case execution time (WCET) is a critical activity in the analysis of real-time systems. Evolutionary algorithms are frequently employed for the determination of worst-case data, used in the estimation of WCET. However, in order to employ an evolutionary algorithm, several executions of the application program are required, either on the target hardware or using its simulator. Multiple executions of the application program consume a huge amount of time. In order to reduce the huge execution time, this paper proposes the use of an adaptive surrogate model. The initial training of surrogate model is performed with a cycle-accurate simulator. The initially trained model is then used to assist the evolutionary algorithm by predicting the execution time of an application program. However, contrary to the direct training approach, the surrogate model in this paper is updated (adapted) during the evolution process. The adaptive training of a surrogate model increases its prediction accuracy and reduces the overall time. The validity of proposed methodology is illustrated with multiple sorting algorithms, extensively used in real-time systems.

EOmesh: Combined Flow Balancing and Deterministic Routing for Reduced WCET Estimates in Embedded Real-Time Systems

The increasing performance needs in critical real-time embedded systems (CRTESs) can only be satisfied with the use of high-performance manycore processors. While NoC-based manycore systems are popular in the high-performance domain due to their high average performance, they challenge deriving tight worst-case execution time (WCET) estimates, as needed in CRTES. Weighted meshes have been proposed to alleviate NoCs pathological behavior—caused by large bandwidth imbalance—by making locally unbalanced arbitration decisions to reach globally balanced bandwidth. In this paper, we show that existing weighted mesh solutions do not completely remove unwanted imbalance, in particular for nodes subject to high congestion. We propose even/odd mesh (EOmesh), an approach that combines heterogeneous predictable routing and weight allocations that delivers near-optimal bandwidth allocation across cores without increasing NoC complexity. EOmesh, which can be implemented either by hardware means or by software means on top of regular weighted meshes, improves the average performance and WCET results of the reference weighted mesh design.

RESEARCH OF LIMIT TIME INDICES OF SOFTWARE ENVIRONMENTS OF REAL TIME OPERATING SYSTEMS

Purpose . More than 20 years of the Worst Case Execution Time (WCET) studies have led to the development of many methods for its evaluation. So far, there are no definitive conclusions about usage of these methods. Therefore, the purpose of this paper is to determine the possibility of using a hybrid method for estimating WCET in systems. Methodology . The approach for evaluating WCET for a hybrid method is to parse the input code in the C++ programming language and, after constructing the control flow graph, get the execution time of its base blocks. After finding the longest way of the graph, to estimate the time of execution of this way and get the WCET evaluation. To find the longest-running way, the reverse Dijkstra algorithm was chosen. After that, there was made a comparison of the limiting time estimations that were obtained by static and hybrid methods, as well as an analysis of the discrepancy between these results. Findings . Determining the worst execution time of programs is most important for hard real-time tasks. Underestimation of this indicator can lead to catastrophic consequences. An overestimation – to a significant overexpenditure of resources. Therefore, WCET was evaluated using static and dynamic methods. It was determined that the results obtained by the two methods correlate well. For the class of tasks that are under consideration, WCET execution time can be determined using a hybrid method. Adding an extra time of 15–20 % to the results, obtained by the hybrid method, allows getting a foolproof estimate of WCET in systems. Originality . The hybrid method has been existing for some time, but the reliability of its use has not been sufficiently studied yet. The given study makes a step in determining the practical applicability of the hybrid method for time estimation of tasks. Practical value . The results of this research allow us to conclude that a hybrid method could be used for obtaining WCET in hard real-time tasks. Furthermore, some unknown at this moment influence of the OS RT environment can be taken into account by adding extra time.

Scalable and precise estimation and debugging of the worst-case execution time for analysis-friendly processors: a comeback of model checking

Estimating the Worst-Case Execution Time (WCET) of an application is an essential task in the context of developing real-time or safety-critical software, but it is also a complex and error-prone process. Conventional approaches require at least some manual inputs from the user, such as loop bounds and infeasible path information, which are hard to obtain and can lead to unsafe results if they are incorrect. This is aggravated by the lack of a comprehensive explanation of the WCET estimate, i.e., a specific trace showing how WCET was reached. It is therefore hard to spot incorrect inputs and hard to improve the worst-case timing of the application. Meanwhile, modern processors have reached a complexity that refutes analysis and puts more and more burden on the practitioner. In this article we show how all of these issues can be significantly mitigated or even solved, if we use processors that are amenable to WCET analysis. We define and identify such processors, and then we propose an automated tool set which estimates a precise WCET without unsafe manual inputs, and also reconstructs a maximum-detail view of the WCET path that can be examined in a debugger environment. Our approach is based on Model Checking, which however is known to scale badly with growing application size. We address this issue by shifting the analysis to source code level, where source code transformations can be applied that retain the timing behavior, but reduce the complexity. Our experiments show that fast and precise estimates can be achieved with Model Checking, that its scalability can even exceed current approaches, and that new opportunities arise in the context of "timing debugging".