Wire Length Research Articles

Wire Load Oriented Analog Routing with Matching Constraints

As design complexity is increased exponentially, electronic design automation (EDA) tools are essential to reduce design efforts. However, the analog layout design has still been done manually for decades because it is a sensitive and error-prone task. Tool-generated layouts are still not well-accepted by analog designers due to the performance loss under non-ideal effects. Most previous works focus on adding more layout constraints on the analog placement. Routing the nets is thus considered as a trivial step that can be done by typical digital routing methodology, which is to use vias to connect every horizontal and vertical lines. Those extra vias will significantly increase the wire loads and degrade the circuit performance. Therefore, in this article, a wire load oriented analog routing methodology is proposed to reduce the number of layer changing of each routing net. Wire load is considered in the optimization goal as well as the wire length to keep the circuit performance after layout, while the analog layout constraints like symmetry and length matching are still satisfied during routing. As shown in the experimental results, this approach significantly reduces the wire load and performance loss after layout with little overhead on wire length.

Investigation of the Corona Discharge Problem Based on Different Computational Approaches of Dimensional Analysis

Although corona discharge is notorious for its detrimental effects, it is also used in many beneficial practical applications. Despite the existence of a variety of sophisticated theoretical and experimental methods for investigating corona discharge, we explore yet a much simpler method that relies on the use of Dimensional Analysis (DA). The DA method does not demand profound knowledge of the underlying phenomenon or its governing equations, as it only needs the correct identification of the variables influencing the phenomenon, and the specification of their physical dimensions. The classical and well-known Gauss-Jordan elimination method is compared with other matrix-oriented computational approaches in analyzing the pertinent dimensional system. This method relies upon solution-preserving elementary row operations, i.e., operations that one can use on a matrix without spoiling the solution set for an associated matrix equation. A distinct advantage of this method is that it does not pre-suppose a particular value of the matrix rank but tackles the task of determining this rank while proceeding towards its ultimate result. Moreover, this method can also be used to find the inverse of a regular (invertible) matrix or to determine the solution (if any) of a system of linear equations. As a bonus, novel results of numerical investigations of bases, regimes, and dimensionless products are extensively presented in this paper. A remarkable observation made herein is that the set of variables pertinent for a particular phenomenon cannot be arbitrarily partitioned into basis (input) variables and regime (output or isolated) variables. The paper running example deals with expressing a specific variable, viz. ozone generation rate per unit length of wire (r0) through dimensionless products in terms of a set of determining or influencing variables.

Giant reversible magnetostriction in a ferromagnet–polymer composite

A magnetostrictive ferromagnet–polymer composite consisting of steel wires suspended in a polymer matrix has been developed that exhibits large reversible magnetostrictive strain in relatively low magnetic fields. The strain for a fixed field is a nonmonotonic function of wire loading for the longer wires investigated, and the strain for a given wire loading increases with decreasing the wire length. Within the limits of this study, a maximum saturation strain of 60.2% in a 7.5 kOe field was observed with a wire length of 0.50 cm and a wire volume fraction of approximately 0.2. No degradation in strain was observed over the maximum number of 50 expansion cycles.

Leakage of Majorana bound states in an inhomogeneous topological nanowire

We present an exact solution of the continuum Bogolyubov-de-Gennes Hamiltonian for Majorana bound states (MBSs) generated in a superconductor–semiconductor hybrid topological nanowire. The full energy spectra that include the band states and in-gap states could be obtained. We show that for relatively short wire length, the zero energy mode could be induced even in the topological trivial regime, which also indicates oscillatory dependence on the chemical potential. With the increase of the Zeeman field, the MBSs are almost fully spin-polarized and do not localize at the wire ends gradually. We also extend our discussion to the property of Majorana modes in an inhomogeneous nanowire, in which a local gate voltage is applied to one end of the nanowire. It is found that the local potential barrier or well could modulate the Majorana energy splitting periodically. The leakage of MBSs to the potential region is exponentially suppressed for the barrier case. A potential well could induce near-zero-energy bound states and these states merge with MBSs, leading to the delocalization of MBSs. In the potential well region, both the spin-up and spin-down components of the trivial states account for a significant proportion, which can be detected experimentally.

Overcoming Rayleigh–Plateau instabilities: Stabilizing and destabilizing liquid-metal streams via electrochemical oxidation

Liquids typically form droplets when exiting a nozzle. Jets--cylindrical streams of fluid-can form transiently at higher fluid velocities, yet interfacial tension rapidly drives jet breakup into droplets via the Rayleigh-Plateau instability. Liquid metal is an unlikely candidate to form stable jets since it has enormous interfacial tension and low viscosity. We report that electrochemical anodization significantly lowers the effective tension of a stream of metal, transitioning it from droplets to long (long lifetime and length) wires with 100-μm diameters without the need for high velocities. Whereas surface minimization drives Rayleigh-Plateau instabilities, these streams of metal increase in surface area when laid flat upon a surface due to the low tension. The ability to tune interfacial tension over at least three orders of magnitude using modest potential (<1 V) enables new approaches for production of metallic structures at room temperature, on-demand fluid-in-fluid structuring, and new tools for studying and controlling fluid behavior.

Novel implementation of 3D multiplexers in nano magnetic logic technology

PurposeOwing to recent challenges of CMOS manufacturing and power consumption in silicon technologies among alternative technologies, Nanomagnetic logic (NML) is one of the most promising technologies, so it was selected for this study. NML is non-volatile with ultra-low power dissipation that operates at room temperature. This paper aims to propose novel implementation of 2% and 4% multiplexers (MUXs) in NML technology.Design/methodology/approachThe proposed multiplexers in NML technology are verified by HDL-based simulators. In addition, this study estimated area and power dissipation of the proposed design to compare and approve the promising improvements in comparison to other similar NML implementations.FindingsThe results show the remarkable improvements in terms of APDP term in comparison to the recent proposed MUXs in NML technology which are reported in Table 2. The proposed implementation of the MUX in NML is designed in three-dimensional layout to improve interconnection complexity which is an integration challenge. Also, by facilitating the routing signals and total wire length needed for clock signals, the negative impact of the power dissipated in clock wires is improved.Originality/valueThese findings would appeal to a broad audience, such as the readership of Microelectronics International Journal. The authors confirm that this work is original and has not been published elsewhere nor is it currently under consideration for publication elsewhere. All authors have approved the paper and agreed with submission to Microelectronics International Journal. The authors have read and have abided by the statement of ethical standards for manuscripts submitted to Microelectronics International Journal. The authors have no conflict of interest to declare.

A simplified voltage model in GMAW

The relation between the voltage and the arc length in gas metal arc welding (GMAW) is an important characteristic. It determines the power transfer to a large extent, and its knowledge allows the control of the process. However, the voltage depends on a complex distribution of the electric conductivity along the current path and does not depend on the arc length only. A simplified electrical model is introduced for a pulsed GMAW process which shows the relation of voltage, current, arc length, and free wire length. It considers also their temporal evolution during the process in particular during the high-current phase. The model is based on previous detailed studies of the sheath voltage and the resistances in the contact tube, the free wire, the droplet depot, and the arc in pulsed processes with changing arc lengths. The electrical model shows a sufficient agreement with electrical measurements and optical estimations of the arc length also for different wire feed speed and different contact-to-workpiece distance (CTWD).

3D Networks of Ge Quantum Wires in Amorphous Alumina Matrix.

Recently demonstrated 3D networks of Ge quantum wires in an alumina matrix, produced by a simple magnetron sputtering deposition enables the realization of nanodevices with tailored conductivity and opto-electrical properties. Their growth and ordering mechanisms as well as possibilities in the design of their structure have not been explored yet. Here, we investigate a broad range of deposition conditions leading to the formation of such quantum wire networks. The resulting structures show an extraordinary tenability of the networks’ geometrical properties. These properties are easily controllable by deposition temperature and Ge concentration. The network’s geometry is shown to retain the same basic structure, adjusting its parameters according to Ge concentration in the material. In addition, the networks’ growth and ordering mechanisms are explained. Furthermore, optical measurements demonstrate that the presented networks show strong confinement effects controllable by their geometrical parameters. Interestingly, energy shift is the largest for the longest quantum wires, and quantum wire length is the main parameter for control of confinement. Presented results demonstrate a method to produce unique materials with designable properties by a simple self-assembled growth method and reveal a self-assembling growth mechanism of novel 3D ordered Ge nanostructures with highly designable optical properties.

SAT-Based On-Track Bus Routing

In modern integrated circuit design, bus routing is a challenge because of complex design rules and wiring constraints. Despite extensive research, state-of-the-art in bus routing is not effective when nonuniform tracks, various obstacles, wire width constraints, and multiple spacing rules should be handled simultaneously. A new bus routing framework proposed in this article is based on maze routing and Boolean satisfiability. It produces high-quality results quickly and allows for additional optimizations, such as minimizing wire length on the critical paths. A number of challenging bus routing benchmarks appeared in 2018 ICCAD Contest. Experiments on these benchmarks not only show that the framework is faster than the winners of the competition and previous work but also produces better results, improving the overall cost by 12% while at the same time minimizing the number of spacing violations.

A two-step routing method with wire length budgeting for PTL routing of SFQ logic circuits

A PTL routing method for large-scale SFQ logic circuits is proposed. In this method, a routing problem is solved in two steps; global routing and detailed routing. In the global routing, a routing region is split into rectangular subregions and paths connecting them are obtained. Wire length budgeting is introduced into the global routing for allocating sufficient amount of routing resources to each net considering wire length matching in the detailed routing. In the detailed routing, exact wiring routes are determined based on a solution of the global routing and wire length matching is performed at each subregion. The global routing with wire length budgeting is formulated and an algorithm for it is proposed. In the proposed global routing algorithm, initial routes are searched at first using the rip-up and reroute technique, and then, routing resource distribution is calculated by constructing a flow-graph and solving a max-flow problem. If distribution of routing resources fails, global route extension is conducted to allocate additional routing resources to nets. The routing resource distribution and the global route extension are repeated until sufficient resources are allocated to all nets. As a design example, a 16 bit Sklansky adder was designed using the proposed method. Wire length matching in detailed routing was succeeded and the target frequency of 50 GHz was achieved.

Stay in tune with a sonic miracle [Sound - Guitar Strings

WITH 2.5 MILLION UNITS sold annually in the US, and the UK pitching in with an extra 750,000, guitars are a billion-dollar business. Which means that the strings that go on them are big business too. If every new American and British six-string had their strings changed at the recommended frequency of once per month, they would in their first year alone consume sufficient length of metal wire to reach the 384,400km it takes to get to the Moon.

Development of Multiobjective High-Level Synthesis for FPGAs

Traditionally, the High-Level Synthesis (HLS) for Field Programmable Gate Array (FPGA) devices is a methodology that transforms a behavioral description, as the timing-independent specification, to an abstraction level that is synthesizable, like the Register Transfer Level. This process can be performed under a framework that is known as Design Space Exploration (DSE), which helps to determine the best design by addressing scheduling, allocation, and binding problems, all three of which are NP-hard problems. In this manner, and due to the increased complexity of modern digital circuit designs and concerns regarding the capacity of the FPGAs, designers are proposing novel HLS techniques capable of performing automatic optimization. HLS has several conflicting metrics or objective functions, such as delay, area, power, wire length, digital noise, reliability, and security. For this reason, it is suitable to apply Multiobjective Optimization Algorithms (MOAs), which can handle the different trade-offs among the objective functions. During the last two decades, several MOAs have been applied to solve this problem. This paper introduces a comprehensive analysis of different MOAs that are suitable to perform HLS for FPGA devices. We highlight significant aspects of MOAs, namely, optimization methods, intermediate structures where the optimizations are performed, HLS techniques that are addressed, and benchmarks and performance assessments employed for experimentation. In addition, we show the analysis of how multiple objectives are optimized currently in the algorithms and which are the objective functions that are optimized. Finally, we provide insights and suggestions to contribute to the solution of major research challenges in this area.

3D printed solution flow type microdroplet cell for simultaneous area selective anodizing

IntroductionRecent advancements in 3D printing technology allow us to design and fabricate customized droplets cells for localized electrochemical patterning. ObjectivesIn this study, 3D printed solution-flow type microdroplet cell (Sf-MDC) is proposed for localized anodizing of two different regions on Al surface. The effect of printing orientation on 3D printing parameters is elucidated to minimize the resin consumption, printing time and material wastage. The capability of Sf-MDC to fabricate porous alumina patterns with adjustable pore size and thickness is explored by varying the length of Pt wire inside each capillary. MethodsThe Sf-MDC was optimally fabricated using 3D printer at the highest possible resolution. The Al specimens were electropolished in 13.6 kmolm−3 CH3COOH/2.56 kmolm−3 HClO4 at 278 K and 28 V for 145 s. 0.22 kmolm−3 oxalic acid (COOH)2 solution was prepared for anodizing. The specimen was set on pulse-XYZ stage controller and anodized (at 50 V and 323 K) using the Sf-MDC. ResultsAnodizing with Sf-MDC resulted in the formation of two uniformly sized porous alumina lines on the specimen. Porous alumina lines exhibited similar pore geometry, interpore distance and pores arrangement, suggesting uniform supply of current to both the droplets. Layered-type cross-sectional structure with each layer having a thickness of 2.7 mm was formed for both the porous alumina lines. By varying the length of Pt wire inside each capillary, porous alumina lines with different porous structure and oxide thickness were simultaneously fabricated. ConclusionsSimultaneous anodizing with Sf-MDC can be applied for fast fabrication of porous alumina filters with different porous structure and for various patterning applications.

Open-channel metals fabricated by the removal of template wires

Abstract

Study on Energy Acquisition Scheme and Parameter Optimization for Double-Insulated Ground Wire of Overhead Transmission Lines

An energy acquisition system for the ground wire of an overhead transmission line can provide a continuous and stable power supply for an on-line monitoring device. Its key issue is how to obtain enough power. To solve this problem, an energy acquisition scheme based on the double-insulated ground wire of an overhead transmission line has been investigated in this study. Three energy acquisition schemes were proposed, equivalent circuit analysis models of the three energy acquisition schemes were established, and the maximum power acquired was theoretically analyzed. The energy acquisition power of the three energy acquisition schemes for different tower-type sizes was also analyzed. A simulation model was built in PSCAD. The effects of load impedance, length of energy acquisition wire, grounding resistance, and load current on the power acquired were analyzed. The research results of this paper provide theoretical guidance for choosing an energy acquisition scheme and for designing key parameters in practice.

Fabricating ultra-sharp tungsten STM tips with high yield: double-electrolyte etching method and machine learning

The double-electrolyte etching method is a simple and effective way to fabricate ultra-sharp scanning tunnel microscopy (STM) tungsten tips. However, it is still challenging for this method to get ultra-sharp tungsten tips with high yield. In this work, significant enhancing of the yield is presented through optimized etching parameters as follows: temperature of 26 °C, applied voltage 7.5 V, electrolyte concentration 4 mol L−1 and length below the liquid lamellae of 2 mm. Under these conditions, the smallest tip radius is around 8 nm and the yield (radius < 10 nm) is 63.5%. These tips are capable of producing high-quality atomic resolution STM images, as demonstrated by testing on Si (111) and highly oriented pyrolytic graphite (HOPG) samples at room temperature. Furthermore, in order to find the relationship between the tip features and experimental etching parameters, an artificial neural network (ANN) model is built by machine learning. Garson’s algorithm is used to analyze the relative importance of each experimental parameter on tip features. The tip features can be estimated by this model with a correlation factor R over 0.85 indicating great predictive performance. Importance analysis indicates that the length of the tungsten wire below the liquid lamellae is the most important parameter to obtain high-quality STM tungsten tips in the double-electrolyte etching method. This result provides a clear direction for rapidly selecting optimized tip fabrication parameters in the future.

Adsorbate induced manipulation of 1D atomic wires: Degradation of long-range order in the Si(553)-Au system

Deposition of Au on vicinal Si(553) surfaces results in the self-assembly of one-dimensional (1D) Au atomic wires. Charge transfer from the Au wire to the Si step edge leads to a chain of Si dangling-bond orbitals with a long range ordered threefold periodicity along the steps and finite interchain interaction perpendicular to the steps. Employing spot-profile analysis low-energy electron diffraction (SPA-LEED) we observed a broadening of spot width with time, indicative for the degradation of Si dangling-bond chain and Au wire length. We introduce a new mechanism how adsorbates act as origin for this degradation beyond the intuitive picture of bond saturation. Here, zero-dimensional anti-phase translational domain boundaries are generated which immediately destroy the long-range order along and perpendicular to the steps, respectively. From the temporal evolution of the decreasing coherence length, we conclude that the Au wires are less reactive to adsorption than the Si dangling bond chains.

Analisis Nilai Hambatan Jenis Aluminium Berdasarkan Panjang Kawat Yang Berbeda

This study aims to determine the value of aluminum specific resistance which is calculated based on Ohm's law. This research uses an experimental method. In this study, 4 experiments were carried out with different lengths of wire. The first experiment used a wire length of 0.05 m, the second experiment used a wire length of 0.1 m, the third experiment used a wire length of 0.15 m, and the fourth experiment used a wire length of 0.2 m. The results of the study showed that the wire length of 0.05 m obtained the value of the type resistance of 2.7 x 10-3 Ωm, the length of the wire of 0.1 m obtained the value of the type resistance of 2.7 x 10-3 Ωm, the length wire of 0.15 m obtained type resistance value of 2.7 x 10-3 Ωm and at a wire length of 0.2 m obtained type resistance value of 2.7 x 10-3 Ωm. Thus, it can be concluded that the change value of aluminum types will be the same value if the wire material used is also the same value.

RETRACTED: A novel optimization approach for partitioning-based place and route in 3D integrated circuits

The 3D integrated circuits are enlarging the technology with lots of potentials which establish vertical interconnection between different dies or layers. In 3D-integrated circuit fabrication, congestion, and wirelength minimization are challenging processes. To overcome these problems, we proposed a novel optimization approach for useful partitioning, placement, and routing. Our proposed work consists of four significant stages, including partitioning, placement, routing, and fault diagnosis in through silicon via and spare through silicon via allocation. Firstly, the QuadTree partitioning method executed by the partitioning process. QuadTree method partitions the layer into four subdivisions and remains until it finds no space for partitioning. AND logic is proposed to overcome the congestion problem during placement. In the second stage, the functioning of the hybrid particle swarm optimization and simulated annealing algorithm proposed by the placement process. Particle swarm optimization computes fitness function for six constraints, specifically wirelength, area, power, cross talk, temperature, and delay. The simulated annealing places circuits in the specified area with the computed fitness function. In every 45°, Kruskal’s based octi-linear Steiner tree algorithm that establishes routes performs the routing by the third stage. In the last stage, fault detection in through silicon via and spare through silicon via allocation processes are executed using the support vector machine algorithm and dedicated switch. Support vector machine classifies the TSV into two, which includes regular and redundant through silicon via. The spare through silicon via allocation performed by using a dedicated switch. Finally, the proposed work evaluated based on metrics such as wire length, area, temperature, delay, and run time.

Miniaturization of a Koch-Type Fractal Antenna for Wi-Fi Applications

Koch-type wire dipole antennas are considered herein. In the case of a first-order prefractal, such antennas differ from a Koch-type dipole by the position of the central vertex of the dipole arm. Earlier, we investigated the dependence of the base frequency for different antenna scales for an arm in the form of a first-order prefractal. In this paper, dipoles for second-order prefractals are considered. The dependence of the base frequency and the reflection coefficient on the dipole wire length and scale is analyzed. It is shown that it is possible to distinguish a family of antennas operating at a given (identical) base frequency. The same length of a Koch-type curve can be obtained with different coordinates of the central vertex. This allows for obtaining numerous antennas with various scales and geometries of the arm. An algorithm for obtaining small antennas for Wi-Fi applications is proposed. Two antennas were obtained: an antenna with the smallest linear dimensions and a minimum antenna for a given reflection coefficient.