Wilkinson Power Combiner Research Articles

A 16.5–28 GHz 0.18-$\mu$m BiCMOS Power Amplifier With Flat $19.4 \pm 1.2$ dBm Output Power

A broadband fully integrated power amplifier (PA) with 3 dB bandwidth from 16.5 to 28 GHz was designed using a 0.18 μm SiGe BiCMOS process. The PA consists of a drive amplifier and two parallel main amplifiers. Lumped-element Wilkinson power divider and combiner are especially used to combine the main amplifiers as well as to provide suppression for the harmonics through their inherent low-pass filtering characteristic. The PA exhibits measured gain of more than 34.5 dB and very flat output power of 19.4±1.2 dBm across 16.5-28 GHz, and power added efficiency (PAE) higher than 20% and 17% between 16-24.5 GHz and up to 28 GHz, respectively. Specifically at 24 GHz, it achieves 19.4 dBm output power, 22.3% PAE, and 37.6 dB gain.

Development of 3 kW at 325 MHz solid-state RF power amplifier using four power amplifier modules

A high power solid-state RF power amplifier of 3kW at 325MHz has been developed using only four RF power amplifier modules of 850W power output each. The design and characterization of RF power modules have been presented. A four way Wilkinson power combiner adds the output of four power amplifier modules with a total transmission loss of less than 6%. The combined power amplifier has a power gain of 20.2dB at 1-dB compression point, and the corresponding output power is 2.8kW at 325MHz. The drain efficiency of the power amplifier is 65.3% at 3kW. All the harmonics of this amplifier are below −40dBc. The amplifier has better characteristics like fewer numbers of active devices per kilo watt, high efficiency, high gain, and ruggedness etc for RF accelerator applications.

A High‐Voltage Driving 60‐GHz Power Amplifier with Psat of 13 dBm and PAE of 9.1% in 90‐nm CMOS for IEEE 802.11ad Communication Systems

ABSTRACTA high‐voltage (3 V) driving 60‐GHz power amplifier (PA) for direct‐conversion transceiver using standard 90 nm CMOS technology is reported. The PA comprises two cascode stages with inductive load and low‐impedance interstage matching, followed by a common‐source output stage. To increase the saturated output power (Psat) and power‐added efficiency (PAE), the output stage adopts a two‐way power dividing and combining architecture. Instead of the area‐consumed Wilkinson power divider and combiner, miniature low‐loss LC power divider and combiner (IL = 0.536 dB @60 GHz) are used. This in turn results in further Psat and PAE enhancement. The PA consumes 176.2 mW and achieves power gain (S21) of 17.9 ± 3.7 dB, input‐port input reflection coefficient (S11) of −5.8 to −7.3 dB, output‐port input reflection coefficient (S22) of −10.4 to −26.3 dB, and reverse isolation (S12) of −56.4 to −81.7 dB for frequencies 50–60 GHz. In addition, for frequencies 50–60 GHz, the PA achieves output 1‐dB compression point (OP1dB) of 6.6–7.8 dBm, Psat of 10.6–13 dBm and maximum PAE of 9.1%, one of the best PAE results ever reported for a 60 GHz CMOS PA. These results demonstrate the proposed PA architecture is very promising for 60‐GHz short‐range communication system applications. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:2033–2039, 2013

A high-performance CMOS power amplifier for 60 GHz short-range communication systems

A 60 GHz power amplifier for direct-conversion transceiver using standard 90 nm CMOS technology is reported.The power amplifier comprises three cascaded common-source stages with inductive load and inter-stage matching. To increase the saturated output power (Psat) and power-added efficiency (PAE), the output stage adopts a two-way power dividing and combining architecture. Instead of the area-consumed Wilkinson power divider and combiner, miniature low-loss LC power divider and combiner are used. This in turn results in further Psat and PAE enhancement. Over the 57 ∼ 64 GHz frequency band of interest, the power amplifier consumes 44.4 mW and achieves power gain (S21) of 12.04 ± 1 dB, input-port input return loss (S11) of −6 to −9.4 dB, output-port input return loss (S22) of −10.4 to −26.4 dB, and reverse isolation (S12) of −29.2 to −30.6 dB. At 60 GHz, the power amplifier achieves Psat of 11.4 mW and maximum PAE of 15.8%. To the authors' knowledge, this is the best PAE ever reported for a 60 GHz CMOS power amplifier. In addition, the measured output 1-dB compression point (OP1 dB) is 6 dBm at 60 GHz. These results demonstrate that the proposed power amplifier architecture is very promising for 60-GHz short-range communication systems. © 2013 Wiley Periodicals, Inc. Microwave Opt Technol Lett 55:1155–1160, 2013; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.27522

A 1 V, 69–73 GHz CMOS power amplifier based on improved Wilkinson power combiner

A 1V, 69–73GHz CMOS power amplifier based on improved Wilkinson power combiner is presented. Compared with the traditional one, the proposed Wilkinson power combiner could lower down the insertion loss and reduce the die area by eliminating the quarter-wavelength transmission lines while preserving the characteristics of Wilkinson power combining and good port isolation. The presented power amplifier has been implemented in 65nm CMOS process and achieves a measured saturated output power of 10.61dBm and a peak power added efficiency of 8.13% at 73GHz with only 1V power supply. The die area including pads is 1.23×0.45mm2, while the power combiner only occupies 200×80μm2.

Design of Vector Modulator Using Low Phase Deviation Attenuators with Large Amplitude Variations Range

In this paper, a novel vector modulator (VM) that precisely controls the magnitude and phase of input signals simultaneously is proposed. The proposed VM consists of low phase deviation attenuators, a 90° hybrid splitter, and Wilkinson power combiner. In order to overcome the phase deviation characteristics found in the conventional attenuators, the novel phase compensation technique has been adopted and mathematically analyzed. Linear vector arrays along the center point with large signal magnitude variations in a full 360° phase control are achieved on a polar plane by the proposed VM.

Concentric Annular-Ring Microstrip Antenna With Circular Polarization

In this letter, we present a concentric annular-ring microstrip antenna that covers the bands of Galileo (E5a, E5b, E1, E2, L1), GPS (L1, L2, L5), and GLONASS (L1, L3). This microstrip antenna is fed by four apertures that improve the coupling. Broad band phase shifters and Wilkinson power combiners are used to generate the required circular polarization.

Photodiodes With Monolithically Integrated Wilkinson Power Combiner

We report the output power and linearity characteristics of two InP/InGaAs partially-depleted-absorber photodiodes monolithically integrated with a Wilkinson power combiner. Compared to a single photodiode an increase of 3 dB in output power is achieved and improved intermodulation distortion, as denoted by the figure of merit, OIP3, is observed in the frequency range up to 20 GHz. We also show that discrete photodiodes with single-stub tuning have improved OIP3 over a frequency range of a few GHz at the expense of reduced output power compared to those without tuning circuits. A model which provides good fits to the frequency dependence of the enhanced OIP3 is developed.

LTCC를 이용한 push-push 유전체 공진 발진기의 설계 및 제작

LTCC(low temperature co-fired ceramic) 공정의 다층기판을 이용하여 push-push 유전체 공진 발전기를 설계 및 제작하였다. 중심주파수 8GHz를 갖는 직렬 궤환형의 단일 유전체 공진 발진기를 설계하고 이를 이용하여 중심주파수 16GHz인 push-push 유전체 공진 발진기를 설계하였다. 발전기의 회로 크기에 큰 영향을 미치는 바이어스 회로를 LTCC 다층구조의 중간층에 배치함으로써 일반적인 단층기판을 이용한 경우에 비해 발진기 회로의 크기를 크게 줄 일 수 있었다. 제작된 push-push 유전체 공진 발진기의 측정결과 기본 주파수 및 3차 고조파 억압특성은 각각 15dBc 및 25dBc 이상의 특성을 나타내었으며 발진기의 위상잡음 특성은 -102dBc/Hz@100KHz 및 -128dBc/Hz@1MHz의 특성을 각각 나타내었다. The push-push DRO(dielectric resonator oscillator) using a multi-layer structure of LTCC(low temperature co-fired ceramic) fabrication is designed. After the single DRO of series feedback type in the center frequency of 8GHz is designed, the push-push DRO in the center frequency of 16GHz including the Wilkinson power combiner is designed. The bias circuit affecting the size of oscillator are embedded in the intermediate layer of the LTCC multi-layer substrate. As a result, the large reduction in the size of VCO is obtained compared to the general oscillator on the single layer substrate. Experimental results show that the fundamental and third harmonics suppression are above 15dBc and 25dBc, respectively, and phase noise characteristics of the push-push DRO presents performance of -102dBc/Hz@100KHz and -128dBc/Hz@1MHz offset frequencies from carrier.

Fundamental wave phase-locked dual-band push-push DRO using out-of-phase Wilkinson power combiner

A new push-push phase-locked dielectric resonator oscillator (PLDRO) with dual-band (C/Ku) output capability is presented. An out-of-phase Wilkinson power combiner is used to provide the fundamental ( f 0 ) output. The phase-locking is implemented at f 0 as an alternative to direct locking the push-push output frequency (2 f 0 ) using prescalers. The push-push PLDRO has shown a fundamental suppression of 35.12 dBc and a second-harmonic suppression of 34.77 dBc at the 2 f 0 output and the f 0 output, respectively. Experimental results also indicate a maximum spur level of -77.4 dBc, and phase noise values of -109.6 and -143 dBc/Hz at 10 kHz and 1 MHz offsets, respectively, from a 12.6 GHz carrier.

A 10–40 GHz Broadband Subharmonic Monolithic Mixer in 0.18 $\mu$m CMOS Technology

A 10-40 GHz broadband subharmonic monolithic passive mixer using the standard 0.18 mum CMOS process is demonstrated. The proposed mixer is composed of a two-stage Wilkinson power combiner, a short stub and a low-pass filter. Likewise, the mixer utilizes a pair of anti-parallel gate-drain-connected diodes to achieve subharmonic mixing mechanism. The two-stage Wilkinson power combiner is used to excite a radio frequency (RF) and local oscillation (LO) signals into diodes and to perform broadband operation. The low-pass filter supports an IF frequency range from dc to 2.5 GHz. This proposed configuration leads to a die size of less than 1.1 times 0.67 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The measured results demonstrate a conversion loss of 15.6-17.6 dB, an LO-to-RF isolation better than 12 dB, a high 2LO-to-RF isolation of 51-59 dB over 10-40 GHz RF bandwidth, and a 1 dB compression power of 8 dBm.

A $Q$-Band Four-Element Phased-Array Front-End Receiver With Integrated Wilkinson Power Combiners in 0.18-$\mu{{\hbox{m}}}$ SiGe BiCMOS Technology

A four-element phased-array front-end receiver based on 4-bit RF phase shifters is demonstrated in a standard 0.18-mum SiGe BiCMOS technology for <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Q</i> -band (30-50 GHz) satellite communications and radar applications. The phased-array receiver uses a corporate-feed approach with on-chip Wilkinson power combiners, and shows a power gain of 10.4 dB with an IIP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> of -13.8 dBm per element at 38.5 GHz and a 3-dB gain bandwidth of 32.8-44 GHz. The rms gain and phase errors are les1.2 dB and les8.7deg for all 4-bit phase states at 30-50 GHz. The beamformer also results in les0.4 dB of rms gain mismatch and les2deg of rms phase mismatch between the four channels. The channel-to-channel isolation is better than -35 dB at 30-50 GHz. The chip consumes 118 mA from a 5-V supply voltage and overall chip size is 1.4times1.7 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> including all pads and CMOS control electronics.

A 28.5–32-GHz Fast Settling Multichannel PLL Synthesizer for 60-GHz WPAN Radio

A 28.5-32-GHz fast settling multichannel frequency synthesizer is implemented in 0.25-mum SiGe : C BiCMOS process technology for 60-GHz wireless personal area network (WPAN) applications. The phase-locked loop (PLL) synthesizes carrier frequencies between 28.5-32 GHz in step of 500 MHz, and settles in approximately 327 ns. The proposed PLL can be employed as a frequency source providing eight channels of frequency hopping carriers for 60-GHz WPAN radio. To generate eight channels of carriers, an integer-N PLL with 125-MHz reference frequency is implemented, and a programmable divider with all differential current-steering circuits is designed. The programmable divider reliably provides divide ratios of 114-128 at 15 GHz. To achieve eight channels of carriers at a challenging frequency of 30 GHz, a push-push voltage-controlled oscillator is employed using a Wilkinson power combiner. The PLL consumes 115 mA at 2.5 V and achieves phase noise of -81 dBc/Hz at 1-MHz offset measured from 32-GHz push-push carrier.

A novel wide-band circularly polarized patch antenna based on L-probe and aperture-coupling techniques

The design and measurements of a wide-band patch antenna with circular polarization are presented. For the proposed antenna, an L-probe and an aperture are utilized to feed the patch orthogonally. The distance between the patch and the ground plane is 0.1 free-space wavelength at 1.8 GHz. Air is used as the dielectric substrate. A Wilkinson power combiner is connected to the feeds to generate circular polarization. The antenna possessed a 14-dB return loss bandwidth of 35% (from 1.49 to 2.12 GHz), and has a 3-dB axial ratio bandwidth of 20.4% (from 1.67 to 2.05 GHz). The 3-dB axial ratio beamwidth and the boresight axial ratio are 84/spl deg/ and 1.94 dB at 1.8 GHz, respectively.

Broadband folded Wilkinson power combiner/splitter

A new folded Wilkinson power combiner/splitter has been realized at millimeter-wave frequency with an area that is one half that of the standard two-stage Wilkinson power combiner. The new splitter has an insertion loss of 5dB, an isolation of 15dB and a return loss 15dB from 15 to 45GHz.

Development of a millimeter-wave system-on-a-package utilizing MCM integration

We present the development of a system-on-a-package at millimeter-wave frequencies utilizing a commercially available multichip-module process. This technology has established a platform for integrating multiple components of different material systems to combine digital application-specific integrated circuits (ASICs), radio-frequency integrated circuits, and microelectromechanical devices onto a package. The multilayer polymer thin films also empower the design and fabrication of integral passive devices, including thin-film resistors, filters, and Wilkinson power combiners.