Wide-locking Range Research Articles

Self-cascode and self-biased Dickson charge pump for fast locking wide lock range PLL with reduced phase noise

The charge pump is a fundamental component in phase-locked loop (PLL) circuits, essential for generating a control voltage that adjusts the frequency and phase of the voltage-controlled oscillator (VCO) to match the input reference signal. The self-cascode and self-biased Dickson charge pump architecture presented in this work addresses several key challenges encountered in conventional PLL designs. By integrating self-cascode techniques, the charge pump exhibits enhanced charging and discharging capabilities, enabling faster locking times essential for wide lock range PLLs. This comprehensive approach offers a compact and integrated solution that simultaneously enhances locking speed, widens the lock range, reduces phase noise, and simplifies design complexity, making it highly suitable for demanding applications in communication systems, radar, and wireless technologies. The novel CP is implemented in 90-nm CMOS technology with a 1.0-V supply voltage. It is integrated with a phase-locked loop (PLL) that has a lock time of 1.0 us, a negligible reference spur, and an average power consumption of 34.7 mW. The PLL is having a wide lock range of 0.98 GHz to 2.98 GHz with a center frequency of 1.54 GHz where the phase noise is calculated to be −100.9 dBc/Hz at 1 MHz offset frequency. This makes the PLL compatible with both GSM having 1.8 GHz and Wi-Fi having 2.8 GHz frequency bands. The proposed PLL is also capable of operating at a wide range of temperatures (−27 °C, 0 °C, 27 °C, 84 °C) and at various corners (NN, FS, SF, SS, FF) making it reliable in adverse circumstances.

A 58-%-Lock-Range Divide-by-9 Injection-Locked Frequency Divider Using Harmonic-Control Technique

This paper presents a divide-by-9 injection-locked frequency divider (ILFD). It can lock onto about 6-GHz input with a locking range of 3.23 GHz (58%). The basic concept of the ILFD is based on employing self-gated multiple inputs into the multiple-stage ring oscillator. A wide lock range is also realized by adapting harmonic-control circuits, which can boost specific harmonics generated by mixing. The ILFD was fabricated using a 55-nm deeply depleted channel (DDC) CMOS process. It occupies an area of 0.0210mm2, and consumes a power of 14.4mW.

A 24.4~39.6 GHz Wide Locking Range Divide-by-4 Injection-Locked Frequency Divider With High Harmonic Rejection Ratio

In this brief, an innovative divide-by-4 injectionlocked frequency divider (ILFD) is hereby proposed to expand the locking range (LR) and improve the harmonic rejection ratio (HRR). Specifically, a fourth-order transformer-based resonator is adopted to improve the LR without any additional tuning capacitors, and a dual-tank network is proposed to optimize the harmonic rejection. To implement the proposed techniques, two chips with different networks are analyzed, designed, and fabricated in a 28-nm CMOS technology. The chip with the dualtank network is proven to achieve the bandwidth from 24.4 to 39.6 GHz, i.e., 47.5% with the second and third harmonic rejection ratios of better than 32 dBc and 11 dBc, while the other chip achieves the bandwidth from 30.8 to 42.6 GHz, i.e., 32.2%. Additionally, the ILFD with the dual-tank network is confirmed to possess differential output power from -17.5 to -19.8 dBm, consuming only 7.4 mW dc power under a 0.5-V supply.

Analysis and Design of Tuning-Less mm-Wave Injection-Locked Frequency Dividers With Wide Locking Range Using 8th-Order Transformer-Based Resonator in 40 nm CMOS

Three tuning-less ultra-wide locking range (LR) transformer-based millimeter-wave (mm-wave) injection-locked frequency dividers (ILFDs) are presented. An eighth-order transformer-based resonator is proposed to improve the LR without an extra tuning mechanism or chip area. The operation principle of high-order transformer-based resonator in ILFDs based on the impedance diagram is analyzed. By comparing different high-order transformer-based resonators, the proposed resonator is the best option for the ultra-wide LR ILFD design. Also, the design considerations and tradeoffs of the implemented resonator are discussed. Furthermore, an inductive gain peaking technique is adopted to ensure start-up conditions and achieve low power consumption. Three ILFDs are designed and fabricated in 40-nm CMOS technology. The first chip exhibits a best-in-class LR of 104.5% from 28.8 to 91.9 GHz while consuming 5.8 mW with a 0.9-V power supply. The second chip achieves the best figure of merit (FoM) up to 26.6 GHz/mW and 79.6% from 31- to 72-GHz LR with a 0.5-V power supply. The third chip obtains an LR of 108.9% from 20 to 67.8 GHz while consuming 4.9 mW with a 0.9-V power supply. Furthermore, 6-dB phase noise differences of the three chips are achieved, which is close to the theoretical value.

Wide locking range frequency tripler based on a dual‐band VCO

A wide locking range (LR) injection locked frequency tripler (ILFT) based on a dual-band voltage controlled oscillator (VCO) is proposed in this Letter. By rationally designing the transformer parameters, the VCO can easily realise the adjacent dual-band operating characteristics. The ILFT has dual LRs which can easily overlap each other at a fixed bias. A subharmonic signal is also injected through the transformer for frequency locking. A wide LR of 27.1% from 69 to 90.6 GHz at an injection power of 0 dBm is achieved whereas the tripler only consumes 5.88 mW under a 0.6 V supply voltage.

Design and analysis of 73-106 GHz CMOS injection-locked frequency divider

ABSTRACT A 73 ~ 106 GHz divide-by-2 injection-locked frequency-divider (ILFD2) using 90 nm CMOS technology is presented. To achieve a wide locking range, an optimal transistor width ratio of the injection transistor (or mixer) and cross-coupled transistors (CCT) is adopted. To enhance the operation frequency, distributed LC network is used as the load of the CCT. To enhance the input sensitivity, an input power matching network is included in the injection transistor. In addition, for further locking ranging enlargement, the inductive peaking and forward-body-bias techniques are used in the injection transistor for raising its quadrature output current (or conversion gain). The ILFD2 consumes 4.92 mW, and achieves an excellent phase noise of – 106.2 dBc/Hz (at 1 MHz offset from the output frequency of 50 GHz). The ILFD2 achieves a wide locking-range of 33 GHz (73–106 GHz (36.9%)), covering the 77 GHz automotive radar frequency band and the 94 GHz imaging radar frequency band. The ILFD2 can be operated at a low input power of – 60 dBm, one of the best input sensitivities ever reported for a W-band CMOS ILFD2. The core area of the ILFD2 is only 0.014 mm2.

A V-Band CMOS Low-DC-Power Wide-Locking-Range Divide-by-6 Injection-Locked Frequency Divider Using Transformer Coupling

A $V$ -band low-dc-power wide-locking-range divide-by-6 injection-locked frequency divider (ILFD) using a 90-nm CMOS process is proposed in this letter. The proposed innovative topology is composed of current-reused oscillation cores with transformer coupling. Moreover, the dc bias of the injectors can be properly applied to widen the locking range (LR). With a core dc power of 5.6 mW and an input power of −5 dBm, the measured maximum locking is 5.6 GHz (9.8%) from 54.5 to 60.1 GHz. When compared to the previously reported $V$ -band ILFDs, this work features a high division ratio, low dc power, wide LR, and good sensitivity.

Wide-Locking Range RLC-Tank Balanced-Injection Divide-by-5 Injection-Locked Frequency Dividers Based on Harmonic Mixing

This article presents and analyzes a wide-locking range divide-by-5 injection-locked frequency divider (ILFD) manufactured in the TSMC 0.18- $\mu \text{m}$ processes. The ILFD uses the balanced injection method and uses the pure harmonic mixing approach at low injection power, and it is designed with an RLC dual-resonance resonator. The harmonic mixer relies on the self-generated second harmonic, which increases with injection power. Because of no narrowband filter as used in the linear mixer counterpart, the divide-by-5 ILFD uses a wideband design method. In addition, the ILFD enhances the divide-by-5 locking range via the overlapped dual-band locking ranges as verified by both experiment and simulation. At the drain–source bias ${V} _{\text{DD}}$ of 0.8 V and at the incident power of 0 dBm, the locking range of the divide-by-5 ILFD is 3.6 GHz, from the incident frequency 13.0–16.6 GHz with the percentage 24.3%. The core power consumption is 4.09 mW, and the die area is $1.02\times0.93$ mm2.

W-band CMOS direct injection-locked frequency divider with 23.5-GHz locking range using distributed LC network and power matching and body bias techniques

A low power and wide locking-range W-band (75–110 GHz) divide-by-2 direct injection-locked frequency-divider (DILFD) using standard 90 nm CMOS technology is reported. To enhance the operation frequency, distributed LC network is used as the load of the crossed-coupled transistors. To improve the input sensitivity, a power matching network is included at the injection terminal of the switch transistor. In addition, to enhance the frequency locking range, body bias technique (i.e. a body resistor in conjunction with a zero body-source bias) is adopted in the switch transistor to reduce its threshold voltage. The result shows that a wide locking-range of 23.5 GHz [from 69.5 to 93 GHz (28.9%)], covering the 77–81-GHz-band for short range automotive radar system and 81–86-GHz-band for high-speed point-to-point wireless communication access system, was achieved. The DILFD can be operated at a low input power of − 35 dBm, one of the best input sensitivity ever reported for a W-band CMOS divider. The power consumption of the DILFD was only 3 mW from a 0.7 V power supply. The chip area was only 0.76 × 0.66 mm2 excluding the test pads.

A 3.1–10.6-GHz 57-Bands CMOS Frequency Synthesizer for UWB-Based Cognitive Radios

An ultra-wideband (UWB)-based cognitive radio (CR) is a promising technique to utilize 3.1–10.6-GHz band efficiently for high data-rate short-range wireless connectivity even in overcrowdedness of the frequency spectrum. Frequency synthesizers tailored to the UWB-based CR should provide wide lock range, multiple frequency bands, and low in-band spurs while consuming low power. This paper investigates a low power, wide lock range, integer-N frequency synthesizer approach with 132-MHz frequency step and 57 subbands in the UWB band. Two-stage supply regulated differential ring oscillator provides linear and wide tuning range with voltage controlled oscillator gain of 22.5 GHz/V and low supply-noise sensitivity. A modular true-single-phase-clock programmable divider achieves wide operating frequency range of 0.1–6.5 GHz and power efficiency of 6.25 GHz/mW by compensating leakage current at the dynamic nodes with conditional latches. Replica-based digital calibration reduces the current mismatch of the charge pump to <1% for low in-band reference spurs of <−60 dBc. A frequency synthesizer test chip was fabricated in 65-nm complementary metal–oxide–semiconductor technology. The active area of the frequency synthesizer is 0.12 mm2. It achieves <−30-dBc integrated phase noise and enables the UWB-based CR to get bit error rate of <10−3 while consuming <−10.1 mW.

Multiple Frequency Digital Phase-Locked Loop Based on Multi-Phase Clock Divider with Constant Pulse Interval

In the mobile communication equipment, the clock generator for driving each system is required to have a fast pull-in time, multiple signal of constant pulse interval, synchronization range, low output jitter, and wide lock-in range characteristics.

Behaviour of fractional loop delay zero crossing digital phase locked loop (FR-ZCDPLL)

ABSTRACTThis article analyses the performance of the first-order zero crossing digital phase locked loops (FR-ZCDPLL) when fractional loop delay is added to loop. The non-linear dynamics of the loop is presented, analysed and examined through bifurcation behaviour. Numerical simulation of the loop is conducted to proof the mathematical analysis of the loop operation. The results of the loop simulation show that the proposed FR-ZCDPLL has enhanced the performance compared to the conventional zero crossing DPLL in terms of wider lock range, captured range and stable operation region. In addition, extensive experimental simulation was conducted to find the optimum loop parameters for different loop environmental conditions. The addition of the fractional loop delay network in the conventional loop also reduces the phase jitter and its variance especially when the signal-to-noise ratio is low.

Adaptive PFD selection technique for low noise and fast PLL in multi-standard radios

Selecting the fast phase frequency detector (PFD) before the loop locks and the low noise PFD after locking, a fast and ultralow noise phase locked loop (PLL) design is achieved in this work. We propose a dual PFD architecture of a PLL which combines the benefits of both the PFDs and heavily shrinks the tradeoffs among phase noise, power consumption and lock time of the PLL. This is achieved by adaptively selecting the PFD at suitable instants of operation of the PLL. Phase noise analysis of the proposed PLL has been carried out and the results of Cadence design simulation are reported for comparison with other standard PLL architectures. The lock time of this PLL is found to be 90ns consuming an average power of 1.2mW for an input reference frequency of 1.25GHz. It also operates over a wide lock range of 0.7–2.8GHz so that it can be used in cellular handsets for multiple radio standards like GSM and WiMAX.

Injection-Locked Frequency Divider Topology and Design Techniques for Wide Locking-Range and High-Order Division

An injection-locked frequency divider topology for wide locking-range and high-order division is presented. Based on the theoretical analysis of the locking-range and injection locking characteristic, we propose locking-range enhancement techniques and high-order dividing topology. Fabricated in a 0.18- $\mu \text{m}$ BiCMOS process, three test circuits are designed with only a standard CMOS, aiming at input frequency ranges of 7.8, 11.1, and 11.7 GHz. The 7.8-GHz divide-by-2 ILFD consumes 2.9 mW with a locking range of 692 MHz operated from a 1.5 V supply. The optimized dual injection method improves the locking range by a factor of 10. The 11.1-GHz divide-by-3 ILFD employs an even-harmonic phase tuning technique and the proposed technique improves the locking range by 25%. The core of the 11.1-GHz ILFD consumes 6.15 mW from a 1.8 V supply. For the 11.7-GHz divide-by-3 ILFD, a self-injection technique is proposed that utilizes harmonic conversion and self-injection to improve phase-noise, locking-range, and input sensitivity simultaneously. By employing harmonic tuning and self-injection, odd-order division is enabled with 47.8% enhancement in the locking-range and 15.7-dBc/Hz reduction in phase noise.

A 285-fsrmsIntegrated Jitter Injection-Locked Ring PLL with Charge-Stored Complementary Switch Injection Technique

An injection-locked ring phase-locked loop (ILRPLL) using a charge-stored complementary switch (CSCS) injection technique is described in this paper. The ILRPLL exhibits a wider lock range compared to other conventional ILRPLLs, owing to the improvement of the injection effect by the proposed CSCS. A frequency calibration loop and a device mismatch calibration loop force the frequency error to be zero to minimize jitter and reference spur. The prototype chip fabricated in 65-nm CMOS technology achieves a 285-fs rms integrated jitter at 3.328 GHz from the reference clock of 52 MHz while consuming 7.16 mW. The figure-of-merit of the ILRPLL is ‒242.4 dB.

Wide-Locking Range Divide-by-3 Injection-Locked Frequency Divider Through Enhanced 2nd Harmonic

Conventional harmonic mixer divide-by-3 ILFD has limited locking range. This letter shows a wide locking range ÷3 ILFD designed with the enhanced 2nd harmonic technique. The proposed ILFD is based on a cross-coupled voltage-controlled oscillator (VCO) and was implemented in the TSMC $0.18 \mu \!\!\text{m}$ 1P6M CMOS process. At the drain-source bias $V_\mathrm{DD}$ of 0.8 V and at the incident power of 0 dBm, the locking range is 4 GHz (50%), from the incident frequency 6 GHz to 10 GHz. The core power consumption is 7.72 mW and the die area is $0.939\times 0.885 \text{mm}^{2}$ .

Wide-Locking Range Divide-by-3 Injection-Locked Frequency Divider Using Sixth-Order &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$RLC$ &lt;/tex-math&gt; &lt;/inline-formula&gt; Resonator

A wide-locking range divide-by- $3~LC$ injection-locked frequency divider (ILFD) is proposed and implemented in the TSMC 0.18- $\mu \text{m}$ 1P6M CMOS process. The divide-by-3 ILFD uses a cross-coupled nMOS pair, an injection MOSFET pair, and a sixth-order $RLC$ resonator. The divide-by-3 ILFD has three oscillation frequency bands and three locking ranges. At the drain-source bias $V_{\mathbf {DD}}$ of 0.9 V and at the incident power of 0 dBm, by switching a varactor bias, the high-band, middle-band, and low-band locking ranges of the ILFD are, respectively, given by 3.47 GHz (33.87%) from 8.51 to 11.98 GHz, 3.72 GHz (54.86%) from 4.92 to 8.64 GHz, and 1.05 GHz (19.76%) from 4.88 to 5.93 GHz. The operation range is 7.1 GHz (84.2%) from 4.88 to 11.98 GHz. The ILFD-core power consumption is 6.759 mW. A wider locking range of 4.43 GHz (67.07%) from 4.39 to 8.82 GHz is obtained by overlapping the three locking ranges at a fixed bias condition. The die area is $0.991 \times 1.04$ mm2.

Triple‐resonance RLC‐tank divide‐by‐2 injection‐locked frequency divider

Conventional CMOS injection-locked frequency dividers (ILFDs) were often designed with a single-resonance LC resonator and they have a single-band locking range. Wide-locking range in these ILFDs was obtained at the cost of lower output power. A triple-resonance (TR) resistor (R), inductor (L) and capacitor (C)-tank ILFD is presented to design a wide-locking range CMOS divide-by-2 circuit, which is based on a cross-coupled n-core MOS pair. The TR ILFD has three overlapped locking ranges seen as one-band locking range at high microwave injection power and it has large output power. At the core power consumption of 6.76 mW and at the microwave input power of 0 dBm, the divide-by-2 TR ILFD achieve a maximum locking range of 5.77 GHz (105.2%) from 2.6 to 8.37 GHz.

Vortex-induced vibration of four cylinders in an in-line square configuration

This paper presents a numerical study of vortex-induced vibration of four rigidly connected and four separately mounted circular cylinders in an inline square configuration at a Reynolds number of 150, a low mass ratio of 2.5, and a range of spacing ratio L from 1.5 to 4, where the spacing ratio is defined as the centre-to-centre distance of two adjacent cylinders normalized by the cylinder diameter. For the rigidly connected cylinder array, the maximum and minimum response amplitudes occur at L = 1.5 and L = 2.0, respectively, for the range of spacing ratio covered in this study and the maximum response amplitude at L = 1.5 is accompanied by a wide lock-in range. The large response amplitude at a small spacing ratio L = 1.5 is because the cylinder array responds to the flow as a single cylinder with an overall size that is much larger than the diameter of the single cylinder while the small response amplitude observed at L = 2.0 is attributed to the strong interaction of the vortices through the gap between the top and bottom rows of the cylinder and also in the wake of the cylinder array. For spacing ratio L ≥ 2.5, the lock-in regime of four rigidly connected cylinders is similar to that of a single cylinder and the response amplitudes in the lock-in regime are slightly higher than that of a single cylinder. The energy transfer analysis between fluid flow and individual cylinders in the array shows that the hydrodynamic forces on individual cylinders either excite or damp the vibration, depending on the reduced velocity. An interesting flow feature observed at L = 2, 2.5, and 3 is the biased vortex street in the wake of four rigidly connected cylinders. The biased vortex street leads to a shift of the mean position of the cylinder array with the largest mean position shift being observed at L = 3. Four response modes are identified for four separately mounted cylinders. These are the in-phase mode, the anti-phase mode, the correlated out-of-phase mode, and the uncorrelated mode. It is found that the response mode chosen by the cylinders is dependent not only on the spacing ratio but also on the initial condition of the flow. The response amplitude under the in-phase mode is generally higher than that under the anti-phase mode at identical spacing ratios. This is attributed to the interaction of vortices in the wake of the cylinders.

A 0.65-to-10.5 Gb/s Reference-Less CDR With Asynchronous Baud-Rate Sampling for Frequency Acquisition and Adaptive Equalization

This paper presents a continuous-rate reference-less clock and data recovery (CDR) circuit with an asynchronous baud-rate sampling to achieve an adaptive equalization as well as a data rate acquisition. The proposed scheme also enables the use of a successive approximation register (SAR) based approach in the frequency acquisition and results in a fast coarse lock process. The CDR guarantees a robust operation of a fine locking even in the presence of large input data jitter due to the adaptive equalization and a jitter-tolerable rotation frequency detector (RFD) that eliminates a dead-zone problem with a simple circuitry. The fabricated CDR in 65 nm CMOS shows a wide lock range of 0.65-to-10.5 Gb/s at a bit error rate (BER) of $10^{-12}$ . The CDR consumes 26 mW from a single supply voltage of 1 V at 10 Gb/s including the power consumption for equalizer. By an adaptive current bias control, the power consumption is also linearly scaled down with the data rate, exhibiting a slope of about 2 mW decrease per Gb/s.