Wide IO DRAM Research Articles

A Real-Time Multichannel Memory Controller and Optimal Mapping of Memory Clients to Memory Channels

Ever-increasing demands for main memory bandwidth and memory speed/power tradeoff led to the introduction of memories with multiple memory channels, such as Wide IO DRAM. Efficient utilization of a multichannel memory as a shared resource in multiprocessor real-time systems depends on mapping of the memory clients to the memory channels according to their requirements on latency, bandwidth, communication, and memory capacity. However, there is currently no real-time memory controller for multichannel memories, and there is no methodology to optimally configure multichannel memories in real-time systems. As a first work toward this direction, we present two main contributions in this article: (1) a configurable real-time multichannel memory controller architecture with a novel method for logical-to-physical address translation and (2) two design-time methods to map memory clients to the memory channels, one an optimal algorithm based on an integer programming formulation of the mapping problem, and the other a fast heuristic algorithm. We demonstrate the real-time guarantees on bandwidth and latency provided by our multichannel memory controller architecture by experimental evaluation. Furthermore, we compare the performance of the mapping problem formulation in a solver and the heuristic algorithm against two existing mapping algorithms in terms of computation time and mapping success ratio. We show that an optimal solution can be found in 2 hours using the solver and in less than 1 second with less than 7% mapping failure using the heuristic for realistically sized problems. Finally, we demonstrate configuring a Wide IO DRAM in a high-definition (HD) video and graphics processing system to emphasize the practical applicability and effectiveness of this work.

Built-In Self-Repair Scheme for the TSVs in 3-D ICs

3-D integration using through-silicon-via (TSV) has been widely acknowledged as one future integrated-circuit (IC) technology. Test and yield are two big issues for volume production of 3-D ICs. In this paper, we propose a built-in self-repair (BISR) scheme to test and repair TSVs in 3-D ICs. The BISR scheme, arranging the TSVs into arrays similar to memories, can effectively enhance the yield of TSVs in a 3-D IC such that the yield of the 3-D IC is boosted. Furthermore, a global fusing methodology is proposed to reduce the requirement of fuses. Simulation and analysis results show that the proposed BISR scheme can drastically reduce the area cost and test time in comparison with an existing TSV repair scheme for the same final yield of TSVs under repair. For a 3-D wide-IO DRAM with 512 TSVs, for example, the proposed repair scheme can achieve 32.4% area reduction and 73.4% test time reduction.

3D Integration of Wide IO Memory Cube Stacking to 28 nm Logic Chip with High Density TSV through a Fabless Supplier Chain

Wide IO memory has higher IO–count (up to 16×) than typical low power DDR memory, which could enable higher system bandwidth at low power. Wide IO DRAM can be stacked as Micro Pillar Grid Array (MPGA) cubes [1], which will provide high memory density for the system. With the high number (∼1200) of connections to the MPGA, a direct face to back stack (3D) to logic chip with high density TSV is the most efficient approach. To utilize the extra large bandwidth, the logic chip containing high speed processors requires logic chip fabrication in advanced node devices. In this paper, we report the–demonstration of a 2-memory chip JEDEC standard wide IO MPGA stacking on logic chip through a fabless supplier chain. A successful integration of via middle through Si via (TSV) to 28 nm logic process has been demonstrated with minimum impact to logic devices. The final package showed good TSV and ubump integrity. The wide IO memory is functional post stacking. In addition, the early reliability data for TSV and ubump showed no detrimental impact through temperature cycle and high temperature storage.