3D Integration of Wide IO Memory Cube Stacking to 28 nm Logic Chip with High Density TSV through a Fabless Supplier Chain

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Wide IO memory has higher IO–count (up to 16×) than typical low power DDR memory, which could enable higher system bandwidth at low power. Wide IO DRAM can be stacked as Micro Pillar Grid Array (MPGA) cubes [1], which will provide high memory density for the system. With the high number (∼1200) of connections to the MPGA, a direct face to back stack (3D) to logic chip with high density TSV is the most efficient approach. To utilize the extra large bandwidth, the logic chip containing high speed processors requires logic chip fabrication in advanced node devices. In this paper, we report the–demonstration of a 2-memory chip JEDEC standard wide IO MPGA stacking on logic chip through a fabless supplier chain. A successful integration of via middle through Si via (TSV) to 28 nm logic process has been demonstrated with minimum impact to logic devices. The final package showed good TSV and ubump integrity. The wide IO memory is functional post stacking. In addition, the early reliability data for TSV and ubump showed no detrimental impact through temperature cycle and high temperature storage.