High Performance 3D Package for Wide IO Memory

Abstract

3D processor-memory packages potentially offer very high performance due to short interconnects between the two chips. Current Package-on-Package (PoP) technology offers less than 300 interconnects between the processor and memory. To meet future bandwidth requirements of greater than 25.8 GB/s bandwidth at low power, wide IO memory in x512 configuration is expected. This memory requires more than 1,000 interconnects and current PoP technologies do not scale to meet these requirements. To address this problem, a new PoP technology called Bond Via Array (BVA) PoP is presented that offers very fine pitch (0.24 mm and lower) and high height/diameter aspect ratio (8:1 and higher). This is achieved by forming free-standing wire-bonds along the periphery of the processor chip and encapsulating the package leaving miniature posts projecting from the top of the package to be connected to the memory package. More than 1,000 interconnects can be formed within the same footprint as current packages. The BVA PoP process development, assembly and reliability test results are presented. The assembly and all reliability tests including Moisture Sensitivity Level (MSL) testing, on-board temperature cycling, high temperature storage, and drop tests were successfully completed. These results demonstrate that the BVA PoP is ready for high volume manufacturing.