Package-on-package with very fine pitch interconnects for high bandwidth

Abstract

Computing platforms are trending towards multi-core and low power processors coupled with high bandwidth memory in close proximity for both client and cloud applications. The most critical feature to keep increasing the performance is the processor-memory interconnect. This is best achieved by placing memory on top of the processor and connecting them through very short and high number of interconnects. However, current 3D packages are limited in number of interconnects primarily due to their low aspect ratio. A new PoP interconnect technology is presented that offers very fine pitch (0.2mm and lower) and high aspect ratio (10:1 and higher), hence enabling high bandwidth between the processor and memory. This is achieved through forming free-standing wire-bonds along the periphery of the processor chip and encapsulating the package leaving miniature posts projecting from the top of the package to be connected to the memory package. It is shown that more than 1000 interconnects can be formed within the same footprint as current packages. The wire-bonds called Bond Via Array (BVA) are Palladium coated copper wires with tips exposed after encapsulation through wet etch techniques. The BVA PoP process development, assembly and reliability test results are presented. The assembly was done at high yield and it successfully completed all reliability tests including MSL, on-board temperature cycling, high temperature storage, and drop tests. These results demonstrate that the BVA PoP is ready for implementation at a high volume manufacturing facility.