Wet Recess Research Articles

(Digital Presentation) A Novel Method For Molybdenum Etching Using a Combination of Surface Oxidation By Ozone-Gas-Bake and Wet Selective Removal for Future Semiconductor Devices

1. IntroductionAlternative metals are being researched to mitigate the resistivity of the metal wiring at 3 nm technology node and beyond. A performance index or figure of merit (FOM) calculated by multiplying the resistivity and the electron mean free path of the bulk metal has been defined to allow the selection of candidate metals to reduce the resistance of fine wiring. Mo (6.0) is a good candidate compared to the conventional metals such as Cu (6.7) and W (8.2) [1-3]. Commodity wet chemistries, e.g. SC-1 or mixed acids like, Phosphoric:Acetic:Nitric-acid (PAN) are not suitable for wet recess etch of Mo since they increase its surface roughness too much. The model for the increase in roughness has been reported to be due to the presence of grain boundaries on the Mo surface, where preferential "oxidation-dissolution" reactions occur simultaneously in the chemical solution [4,5]. To minimize the roughness, a new cyclic process of dry oxidation and wet etching is developed so that oxidation and etching reactions are separated. In the oxidation step, a homogeneous oxide layer is formed by baking in ozone (O3) gas, then it is selectively etched by subsequent wet chemistry which doesn’t contain any oxidant [6]. In this paper, we report the development of this molybdenum recess process with a higher baking temperature to increase the recess depths, targeting application of buried power rail in logic and word line recess in 3D NAND memory.2. ExperimentalSample: 50 nm Mo films were deposited by Plasma Vapor Deposition on a 100 nm SiO2 film. After metal deposition, the wafers were annealed for 20 minutes at 420°C in pure N2 gas.Etching process: oxidation process is performed in an O3 gas chamber on a single wafer cleaning tool. Bake plate in the O3 gas chamber was heated to 180-290°C. O3 concentration was 100 g/m3 and gas flow rate was 18 L/min. The subsequent wet etch process was performed in wet process chamber on the same tool. 29% NH4OH was mixed with ultrapure water in a 1:8 or 1:100 volume ratio at RT or 70°C.Characterization: the recess amounts of metallic Mo and MoOx thicknesses were measured by sheet resistance measurements and mass measurements of 300 mm wafers. Roughness was measured by Atomic Force Microscope, XSEM was used to validate the above. The polycrystallinity of MoOx was analyzed by Grazing Incidence X-ray Diffraction.3. Results/DiscussionMo thickness decreases as the number of oxidation and etching cycles increases, and the recess amount per cycle was 6 nm at 290°C (Fig. 1). The recess amount per 3 cycles increased as bake temperature increases (Fig. 2). Rq increased from 0.4 nm to 2.8 nm at bake temperatures ≥ 250°C (Fig. 3). XSEM showed that the cause of the surface roughness is residual MoOx (Fig. 4). XRD showed that the MoOx changes significantly at bake temperatures ≥ 250°C since other than the metallic crystalline Mo peak at 2θ = 40° were detected, which suggests that polycrystalline MoOx is formed at high temperature (Fig. 5). The formation of a polycrystalline MoOx could be the cause of the surface roughness because these MoOx are tough to dissolve and therefore the surface would not be recessed evenly. On the other hand, the residual MoOx was etched by NH4OH in a 1:8 ratio at 70°C and Rq was reduced to 0.38 nm after a cyclic process using a 290°C bake with O3 (Fig. 3, 4).4. ConclusionA novel etching method using a combination of “ozone-gas-bake” and “wet selective removal” was developed to overcome the roughness increase during etching of Mo observed with commodity wet chemistries. This method demonstrates good controllability of Mo etching amount by changing the number of cycles without roughening the surface. The surface roughness increased at bake temperatures ≥ 250°C due to the formation of polycrystalline MoOx that could not be removed with the conventional NH4OH solution, but this was mitigated by increasing the temperature of the subsequent NH4OH oxide dissolution step. This new process is expected to be used to recess Mo in logic and memory devices for next generation applications.

Wet Chemical Recess Etching of Ge2Sb2Te5 for 3D PCRAM Memory Applications

Memory cells comprising a Phase Change Material (PCM) are the building blocks of fast and non-volatile memory devices called Phase Change Random Access Memory (PCRAM) [1-3]. The working principle of this memory involves data retention in the form of a phase (amorphous or crystalline) and the set and reset can be done by Joule heating to induce an amorphous-to-crystalline or crystalline-to-amorphous transition respectively. Some chalcogenide materials experience this thermally driven phase change, GeSbTe (GST) being one of those alloys extensively studied. GST has also been adopted for the fabrication of the 1st generation X-point memory [4] and might be adopted in a 2nd generation X-point memory of a four-layer PCM structure [5]. However, this 2D scaling or stacking of PCRAM is limited by cost and therefore the development of 3D architectures is envisaged for decreasing the cost/bit [6].A key requirement for the fabrication of this 3D architecture is the conformal deposition and etch-back of GST. Dry plasma etching might be limited to anisotropic recess while isotropic lateral recess is needed. Therefore, wet isotropic etching might be the process of choice. A few chemical solutions have been proposed in previous studies. Cheng et al. showed that GST could be etched in HNO3 but with a very high etch rate and with an unwanted surface composition change due to different oxidation and dissolution rates of the metalloids [7]. Wang et al. demonstrated that basic wet etching solutions led to a slower etch rate and a much smoother surface compared to acidic wet etching solutions [8]. Deng et al. showed a switch in the etch rate order between crystalline and amorphous GST depending on the H2O2 concentration in TMAH [9].In this work, we present a controllable partial recess solution that leaves the GST surface smooth after recess. Wet recess of amorphous and crystalline blanket films, as well as patterned samples, was initially explored using the commodity chemistries Ammonium Peroxide Mixture (APM) and (Hydrochloric Peroxide Mixture) HPM. The etching of GST in HPM as a function of the H2O2 concentration was monitored by ICPMS and showed a well-controlled etch rate. However, some shortcomings of these H2O2-containing solutions, like roughness and selectivity, lead to a change of oxidizing agent from H2O2 to O3. In the O3-containing solutions, the selectivity towards Al2O3, SiO2, and TiN could be secured. The impact of the dissolved O3 concentration on surface roughness and etch rate as well as the uniformity of this wet etching process were assessed on a single wafer tool. Finally, the bulk and surface GST composition and oxidation post-recess were verified through XPS and ERD.REFERENCES:[1] D. Loke et al., “Breaking the Speed Limits of Phase-Change Memory.” Science, 2012, 336, 6088, 1566.[2] K. Ding et al., “Recipe for ultrafast and persistent phase-change memory materials.” NPG Asia Mater 12, 63, 2020.[3] F. Rao et al., “Reducing the stochasticity of crystal nucleation to enable sub-nanosecond memory writing.” Science, 2017, 358, 6369, 1423.[4] [internet] https://www.techinsights.com/blog/intel-3d-xpoint-memory-die-removed-intel-optanetm-pcm-phase-change-memory [5] [internet] https://www.techinsights.com/blog/memory/intels-2nd-generation-xpoint-memory [6] [internet] https://www.imec-int.com/en/imec-magazine/imec-magazine-october-2017/in-pursuit-of-high-density-storage-class-memory [7] H.Y. Cheng et al., “Wet-Etching Characteristics of Ge2Sb2Te5 Thin Films for Phase-Change Memory.” IEEE Trans. Magn., 41, 2, 2005.[8] L. Wang et al., “Basic Wet-Etching Solutions for Ge2Sb2Te5 Phase Change Material.” J. Electrochem. Soc., 157, H470, 2010.[9] C. Deng et al., “XPS study on the selective wet etching mechanism of GeSbTe phase change thin films with TMAH.” Proc. of SPIE, 8782, 87820N, 2012.

Demonstration of High Interface Quality AlGaN/GaN MIS-HEMT with Fully Wet Recess and MOCVD Grown AlN Dielectric

In this study, the results indicate that a method combining fully-recessed wet etching and regrown channel by MOCVD is capable of obtaining high quality interface in GaN MIS-HEMT. A low Vth hysterisis GaN MIS-HEMT of 0.3V is demonstrated in this work. The GaN MIS-HEMT has a Vth of-1.5 V, a high Id,max of 771mA/mm and a RON of 13.5 Ω·mm. The wet etching shows good uniformity while the MOCVD grown AlN enhances the maximum drain current. The concept provides new insights to gate recess fabrication and MOCVD grown high quality dielectrics.

Normally-off AlGaN/GaN-based MOS-HEMT with self-terminating TMAH wet recess etching

Normally-off AlGaN/GaN-based MOS-HEMT has been fabricated by utilizing damage-free self-terminating tetramethyl ammonium hydroxide (TMAH) recess etching. The device exhibited a threshold voltage of +2.0 V with good uniformity, extremely small hysteresis of ∼20 mV, and maximum drain current of 210 mA/mm. The device also exhibited excellent off-state performances, such as breakdown voltage of ∼800 V with off-state leakage current as low as ∼10−12 A and high on/off current ratio (Ion/Ioff) of 1010. These excellent device performances are believed to be due to the high quality recessed surface, provided by the simple self-terminating TMAH etching.

High Electron Mobility Transistors Yield Improvement with Ultrasonically Assisted Recess for High-Speed Integrated Circuits

InAlAs/InGaAs high electron mobility transistors (HEMTs) have been a great contribution to the research and development of high-speed integrated circuits, owing to their high electron mobilities, high saturation velocities, and high sheet electron densities. In integrated circuits using a HEMT as active device, the gate recess process has considerable influence on the yield and uniformity. The wet recess of a 0.1 µm gate footprint has difficulty achieving a high yield greater than 98% due to a nonuniform reaction between the etchant and the semiconductor. A uniform initial reaction between the InGaAs cap layer and the wet etchant mainly determines the yield and uniformity. In this paper, we present an ultrasonically assisted recess method of promoting a uniform initial reaction in the recess process. This method enables us to achieve a high yield and a high uniformity in integrated circuits.

Super low noise InGaP gated PHEMT

Very high performance InGaP/InGaAs/GaAs PHEMTs will be demonstrated. The fabricated InGaP gated PHEMTs devices with 0.25 × 160/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 0.25 × 300 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of gate dimensions show 304 mA/mm and 330 mA/mm of saturation drain current at V/sub GS/ = 0 V, V/sub DS/ = 2 V, and 320 mS/mm and 302 mS/mm of extrinsic transconductances, respectively. Noise figures for 160 μm and 300 μm gate-width devices at 12 GHz are measured to be 0.46 dB with a 13 dB associated gain and 0.49 dB with a 12.85 dB associated gain, respectively. With such a high gain and low noise, the drain-to-gate breakdown voltage can be larger than 11 V. Standard deviation in the threshold voltage of 22 mV for 160 μm gate-width devices across a 4-in wafer can be achieved using a highly selective wet recess etching process. Good thermal stability of these InGaP gated PHEMTs is also presented.

Gate Orientation Dependence of InGaAs/AlGaAs High Electron Mobility Transistors Formed by Wet Recess Etching

The gate orientation dependence of InGaAs/AlGaAs high electron mobility transistors (HEMTs) formed by the wet-chemical recess etching has been evaluated. The short channel effect strongly depends on the gate orientation and is significant in the order of [011], [001] and [011] oriented devices. Such orientation dependence results from a difference of the side-etching lengths, which are 0.01 µm, 0.03 µm and 0.06 µm for the [011], [001] and [011] oriented devices, respectively. The other characteristics of HEMTs such BVgd, gm and fT also depend on the gate orientation because of a difference of the recessed shape.

Highly Selective GaAs/Al0.2Ga0.8As Wet Etch Process for the Gate Recess of Low-Voltage-Power Pseudomorphic High-Electron-Mobility Transistor

A selective wet etch process for the gate recess of the GaAs power pseudomorphic high-electron-mobility transistors (pHEMT's) was developed. The power pHEMT's used in this study were epitaxially grown power Al0.2Ga0.8As/In0.2Ga0.8As pHEMT's with a 250 Å GaAs cap layer and a 300 Å Al0.2Ga0.8As electron-donating layer. The electron-donating layer was used as the etch-stop layer for the gate recess. A selectivity of 3400:1 was achieved for GaAs/Al0.2Ga0.8As layers using citric acid/tripotassium citrate/hydrogen peroxide etching solutions in this study. This is the highest selectivity for GaAs/AlxGa1-xAs selective etching reported so far. The pHEMT's processed using this selective etching demonstrated good device power performance, and the wet recess process did not cause any contamination or damage to the device. The test data indicates that this selective etch process can be of practical use for forming the gate recess of the power pHEMT's with good device performance and excellent electrical uniformity.

Low excess noise of InAlAs/InP HFETs fabricatedusing selective dry recess etching

The low frequency noise (10 Hz-100 kHz) behaviour of InAlAs/InP HFETs fabricated using CH/sub 4//H/sub 2/ selective dry recess etching is reported. Devices from the same epitaxial structure fabricated using wet recess etching are also presented for comparison. The dry etching technique improves the drain noise spectral density. This improvement is attributed to the decrease in the source and drain resistance from 2.4 /spl Omega/ mm for the wet recess, to 1.6 /spl Omega/ mm For the dry recess. The equivalent series resistance fluctuations can explain the noise behaviour in both devices. No significant passivation of traps occurs during the CH/sub 4//H/sub 2/ etching process, as demonstrated by noise measurements on annealed dry etched devices.

High-performance Ka-band monolithic low-noise amplifiers using 0.2-μm dry-recessed GaAs PHEMTs

Ka-band ultra-low-noise amplifiers fabricated with a manufacturable dry-recess process are presented. Low-damage selective dry etching was used for gate recess to achieve uniform threshold voltage (Vth) and saturation current (I/sub dss/). Threefold improvement in Vth uniformity was achieved in comparison with the wet recess process. Fabricated PHEMT low-noise amplifiers (LNAs) employing 0.2-μm mushroom gates showed an average noise figure of 2.2 dB from 31-36 GHz with an associated gain of 22.5 dB. At the design frequency of 35 GHz, the noise figure was less than 2 dB. This is among the best results ever reported for Ka-band LNA's.

Enhancement-mode buried gate InGaP/AlGaAs/InGaAsheterojunction FETs fabricated by selective wet etching

Enhancement-mode buried gate InGaP/AlGaAs/InGaAs heterojunction FETs (HJFETs) were successfully fabricated by using a highly-selective wet recess etching technique. The fabricated HJFET exhibited a maximum drain current of 202 mA/nm, a peak transconductance of 330 mS/mm and a gate-drain breakdown voltage of 33 V. Standard deviation of the threshold voltage was 60 mV, which is less than one fifth that of the conventional AlGaAs/InGaAs HJFET. No appreciable frequency dispersion in the drain current was measured, indicating that the developed InGaP/AlGaAs/InGaAs HJFET with a buried gate structure is promising for large-signal microwave power applications.

Very low damage etching of GaAs

A very low damage, anisotropic and selective reactive ion etching process has been developed using SiCl4 for etching GaAs which stops on extremely thin GaAlAs layer (4 monolayers 1.13 nm thick). Using low rf powers of ≤15 W, and hence low dc biases of 40 to ≤70 V, pressures of 8 mTorr and flow rates of 4–6 sccm, the damage was kept to a minimum value while maintaining very good anisotropy. Both the surface and sidewall damage were measured and the results were confirmed by evaluation of the performance of a metal–semiconductor field effect transistor (MESFET) with a recessed gate. Raman scattering studies of the etched surface of a heavily doped GaAs layer show that the surface damage thickness is only 3–4 nm after 2 min of etching. The damage depth increases and saturates at 9 nm after 4 min of etching (etch rate of ∼100 nm/min). Conductance measurements [S. Thoms, S. P. Beaumont, C. D. W. Wilkinson, J. Frost, and C. R. Stanley, in Microcircuit Engineering, edited by H. W. Lehman and Ch. Bleicher (North Holland, Amsterdam, 1986), p. 249] of narrow wires formed in n+-GaAs by etching at dc biases of 40–70 V show that the sidewall damage is negligible (1 nm/sidewall) after the first 2 min of etching. This value increases to 5 nm/sidewall after 3 min etching and to 12 nm/sidewall after 5 min. This is far lower than the value 18 nm/sidewall obtained by etching for 2 min at dc biases of 200 V. Control of the transconductance of the GaAs MESFETs by wet recess etching is difficult. Dry etching to a thin stop layer is a better method, provided it is damage-free. A ratio of etching rates of GaAs: Ga0.7Al0.3As of ≳10 000:1 on a 4 monolayer thick Ga0.7Al0.3As was obtained. On existing FET device wafers with a 5 nm GaAlAs stop layer, after 2 min etching which is sufficient to come to the stop layer, the transconductance was 4.02 mS, after 5 min etching was 3.67 mS and after 12 min was 2.05 mS. Optical emission spectroscopy revealed that the dominant emitting species in the plasma are Si, SiCl, SiCl2, and Cl. The variation of emission intensity of these species with power reveals clearly the presence of two distinct etch mechanisms, one below and one above 15 W (0.066 W/cm2) power density. The etch rate does not increase monotonically with power.

Dry etching bilayer and trilevel resist systems for submicron gate length GaAs based high electron mobility transistors for power and digital applications

Dry-etching technologies for submicron gate recess and resist pattern transfer are demonstrated with bilayer and trilevel resist systems for power and digital applications, respectively. For power applications, damage-free, dry-etched 0.25 μm T-shaped gate pseudomorphic InGaAs channel high electron mobility transistors (HEMTs) were fabricated. A Freon-12 based discharge was used in either electron cyclotron resonance or reactive ion etching systems to perform the gate recess process. Etching selectivity of more than 200 was obtained between the GaAs cap layer and the underlying AlGaAs donor layer. Self-bias voltages of −30 to −50 V were used in the etching process to minimize the damage. Pre- and postetch clean steps were utilized to achieve uniform etch and removal of any dry etch related residues. By using the dry etch for gate recess, very tight threshold voltage uniformity across a quarter of a three inch wafer of ±85 mV was obtained in comparison to ±500 mV with our conventional wet recess technology. The extrinsic transconductance was 437 mS/mm with output conductance of 10 mS/mm. With a trilevel resist system, AlGaAs/GaAs single and double heterostructure [high field effect transistors (HFETs) and single quantum wells (SQWs)] were also fabricated as well as pseudomorphic AlGaAs/InGaAs/GaAs [pseudomorphic HEMTs (PHEMTs)] heterojunction FETs to investigate the scaling of the direct-current performance with gate length for high speed digital applications. Electron-beam lithography was used to define the gate length from 1 to 0.1 μm. The PHEMT had a consistently higher voltage gain at all gate lengths, with a voltage gain of greater than 30 for a gate length of 0.1 μm.