Dry etching bilayer and trilevel resist systems for submicron gate length GaAs based high electron mobility transistors for power and digital applications

Abstract

Dry-etching technologies for submicron gate recess and resist pattern transfer are demonstrated with bilayer and trilevel resist systems for power and digital applications, respectively. For power applications, damage-free, dry-etched 0.25 μm T-shaped gate pseudomorphic InGaAs channel high electron mobility transistors (HEMTs) were fabricated. A Freon-12 based discharge was used in either electron cyclotron resonance or reactive ion etching systems to perform the gate recess process. Etching selectivity of more than 200 was obtained between the GaAs cap layer and the underlying AlGaAs donor layer. Self-bias voltages of −30 to −50 V were used in the etching process to minimize the damage. Pre- and postetch clean steps were utilized to achieve uniform etch and removal of any dry etch related residues. By using the dry etch for gate recess, very tight threshold voltage uniformity across a quarter of a three inch wafer of ±85 mV was obtained in comparison to ±500 mV with our conventional wet recess technology. The extrinsic transconductance was 437 mS/mm with output conductance of 10 mS/mm. With a trilevel resist system, AlGaAs/GaAs single and double heterostructure [high field effect transistors (HFETs) and single quantum wells (SQWs)] were also fabricated as well as pseudomorphic AlGaAs/InGaAs/GaAs [pseudomorphic HEMTs (PHEMTs)] heterojunction FETs to investigate the scaling of the direct-current performance with gate length for high speed digital applications. Electron-beam lithography was used to define the gate length from 1 to 0.1 μm. The PHEMT had a consistently higher voltage gain at all gate lengths, with a voltage gain of greater than 30 for a gate length of 0.1 μm.