Weak Inversion Regions Research Articles

A Robust and Scalable Constant-$g_m$ Rail-to-Rail CMOS Input Stage With Dynamic Feedback for VLSI Cell Libraries

In this paper, we propose a robust and scalable constant- rail-to-rail CMOS input stage for VLSI cell libraries. The proposed circuit does not rely on the characteristics and particular operation (strong, moderate, and weak inversion) regions of the input transistors and is insensitive to mismatches between p- and n-channel devices. Only standard CMOS transistors are used in the circuit without any special devices, such as floating-gate or depletion-mode transistors. Very small variations (less than ) have been achieved without sacrificing the large-signal behavior. The proposed circuit is proven effective for both long-channel and deep sub-micron CMOS technologies and is suitable for VLSI cell libraries, audio/video, embedded mixed-signal system-on-chip (SoC), and other applications. A prototype amplifier with rail-to-rail input common-mode range has been designed and fabricated in a standard 0.35-m CMOS technology. Experimental results confirm the effectiveness and robustness of proposed techniques.

A Short Story of the EKV MOS Transistor Model

The EKV MOS transistor model and design methodology evolved from the first weak inversion transistor models of the 1970's. In this first-hand account, Christian Enz chronicles the evolution of the hierarchical structure, limited parameters and flexibility of the EKV model that he developed with colleagues such as Francois Krummenacher and Eric Vittoz (the "E" "K" and "V" of EKV) at the Centre Electronique Horloger (CEH) in Neuchatel. With the aggressive downscaling of CMOS technologies today, the EKV compact model is shifting increasingly from the traditional strong inversion region toward moderate and weak inversion regions.

Modelling charge injection in MOS analogue switches using a compact model in a deep submicron technology

Charge injection in MOS switches in a deep submicron technology has been analysed. The analysis has been extended to the general case of including the conduction of the MOS transistor in the moderate and weak inversion regions, using a continuous and physical formulation based on the EKV model. SPICE simulations, based on the BSIM3v3 model, which ensures the charge conservation, have demonstrated the validity of our work.

A CMOS transconductor with multidecade tuning using balanced current scaling in moderate inversion

A versatile CMOS transconductor is proposed. Voltage-to-current conversion employs a polysilicon resistor and features high linearity over a wide input range and high current efficiency. Programmable balanced current mirrors able to operate in weak or moderate inversion regions provide wide transconductance gain tuning range without degrading other performance parameters like input range and linearity. The transconductor has two degrees of freedom for gain tuning. A 0.5-/spl mu/m implementation achieves a SFDR of 68 dB and a THD of -66.5dB using a dual supply of /spl plusmn/1.3 V with differential input swings equal to 77% of the total supply voltage, transconductance tuning over two decades, and 1.7 mW of static power consumption. Measurements demonstrate that operation in moderate inversion can lead to much less distortion levels than in strong inversion.

Analytical Model of the Effects of a Nonuniform Distribution of Stored Charge on the Electrical Characteristics of Discrete-Trap Nonvolatile Memories

We propose an analytical model of the effects of a nonuniform distribution of trapped charge on the electrical characteristics and on the perspectives of 2-bit operation of discrete-trap memories. To keep the model tractable, we consider an idealized nonuniform distribution, represented by a step function, so that the concentration of trapped charge can assume only two possible values in two different regions. Notwithstanding the simplicity of our assumptions, which limits the range of validity of our model to the subthreshold and weak inversion regions of the I-V characteristics, we can investigate a series of important aspects for 2-bit storage of nonvolatile memories. Our model is then validated through comparison with detailed numerical simulations performed with a commercial technology computer-aided design tool, and with the experimental electrical characteristics of nanocrystal flash memories under different bias conditions. Finally, we provide a method, based on our model, to extract an "effective" distribution of trapped charge, in which all charge is uniformly distributed in a localized region close to the drain.

MOS table models for circuit simulation

Compact MOSFET models for circuit simulation face several competing requirements, such as fast execution times, good accuracy and small memory requirements. This paper describes novel interpolation methods for accurate evaluation of MOSFET characteristics in weak, moderate, and strong inversion regions. These methods form the basis of a new table look-up model implemented in SPICE3F5. The table model provides great flexibility in adjustment of the simulation accuracy, speed, and memory consumption by providing a choice of interpolations and data tables. Application of the model to circuit simulation gives very accurate results in dc, transient, and ac analyses.

Using the weak inversion region to optimize input stage design of CMOS op amps

Operation of MOS devices in the strong, moderate, and weak inversion regions is considered. The advantages of designing the input differential stage of a CMOS op amp to operate in the weak or moderate inversion region are presented. These advantages include higher voltage gain, less distortion, and ease of compensation. Specific design guidelines are presented to optimize amplifier performance. Simulations that demonstrate the expected improvements are given.

A unified model for high-frequency current noise of MOSFETs

At high frequency, the MOSFET drain current noise and induced gate noise are generally accepted as dominated by the thermal noise as the MOSFET is operating in strong inversion region. However, controversy exists about the high-frequency noise in subthreshold region. This paper proposes unified high-frequency drain current noise and induced gate noise models valid in strong-, moderate- and weak-inversion regions. These models are necessary for the completeness of device noise model and helpful for low-noise high-frequency amplifier design with deep submicrometer technologies with MOSFETs operating in moderate inversion region.

An explicit expression for surface potential at high-end of moderate inversion

There is a moderate inversion region between the weak and strong inversion regions of MOSFET operation. This region is very important for designing analog circuits. This paper presents a new explicit expression for the surface potential at the high-end of the moderate inversion, which is useful for a circuit modeling. This expression allows a new definition for the threshold voltage V/sub th/ and a model of the relation between off-current I/sub off/ and on-current I/sub on/ of MOSFETs. A source resistance R/sub s/ has large influence on I/sub on/, so that a model for R/sub s/ was newly developed. Proposed models for V/sub th/ and I/sub off/-I/sub on/ characteristics were compared with experiments. It is found that the new definition Of Vth could apply to both short- and long-channel MOSFETs. The model revealed different I/sub off/-I/sub on/ behaviors between high and low halo dose MOSFETs.

A dc charge sheet turn-on model for the I–V characteristics of doped polysilicon thin film transistors

An explicit semi-empirical analytical model for surface potential is proposed for doped polysilicon thin film transistors (poly-Si TFTs). The model shows good agreement with numerical calculation of surface potential in the weak and strong inversion regions. Further, a surface-potential-based dc charge sheet turn-on model is also proposed for small grain doped poly-Si TFTs. The validity of the model is tested by using measured ID–VDS and ID–VGS data for n-channel doped poly-Si TFTs. The results show that the drain current in the device is predicted by the model with good accuracy. Although the model does not consider the grain boundary potential barrier ΨB explicitly, the validity of the model is attributed to the fact that in the turn-on region the gate voltage is sufficiently high resulting in a decrease of ΨB to low values and thus not affecting the drain current significantly. The model also considers the kink effect which becomes dominant at higher drain to source voltage.

A new charge model including quantum mechanical effects in MOS structure inversion layer

Based on the analysis of the distribution of inversion layer carriers in MOS structure, the concept of surface layer effective density-of-states (SLEDOS) is proposed. Then a new charge control model suitable for both semi-classical and quantum mechanical theory is established in which the effects of inversion layer carrier distribution on surface potential are included. In this model, a newly developed efficient iteration method is introduced, which has high efficiency and satisfied stability. Based on the model, the effects of quantum mechanical effects (QMEs) on inversion layer charge density both in weak and strong inversion regions and the surface potential are studied. Model results are compared with the self-consistent solutions of Schrodinger and Poisson equations, which proves the high accuracy of the new model.

A compact and unified MOS DC current model with highly continuous conductances for low-voltage ICs

A unified approach for the MOS transistor drain current modeling through all the operation regions is presented. Instead of the direct sum approach, the proposed use of interpolation and sigmoid functions can unify the drain current expression including the drift and diffusion components for the weak- and strong-inversion regions. This approach results in a differentiable continuity in conductances with respect to the gate, drain, and bulk bias voltages. As verified by the experimental data, the model shows an accurate prediction capability for the transconductance and output conductance characteristics in both strong- and weak-inversion regions.

A Unified Approach to Submicron DC MOS Transistor Modeling for Low-Voltage ICs

A unified single-equation approach for the MOS transistor drain current modeling for energy-efficient submicron MOS circuits is presented. Instead of three sets of separate equations for the triode, saturation, and weak inversion regions, only a continuous expression which is valid to describe the behavior of drain current and the derivatives in all operation regions can be realized by using a combination of hyperbola, sigmoid, and interpolation methods. The model expression can predict accurate results for the current, output conductance, and transconductance with continuous and smooth characteristics. The simulation results agree well with experimental data.

A submicron DC MOSFET model for simulation of analog circuits

This paper presents an efficient dc MOSFET model for accurate simulation of analog circuits. A new approach to model channel length modulation is presented. An empirical expression for channel length modulation is derived from measurements. This is used to model the observed behavior of g/sub D/ with gate, drain, and substrate bias. Some of the models commonly used for circuit simulation do not predict the effects of gate and substrate bias adequately. A new smoothing function is used to unify the linear and saturation regions in a single expression. Continuity of transconductance is maintained between the weak and strong inversion regions. Model efficiency is maintained by avoiding the use of transcendental functions in the smoothing techniques. We demonstrate >

PCIM: a physically based continuous short-channel IGFET model for circuit simulation

We present an accurate analytical IGFET model (PCIM), for short-channel devices down to sub-half micron channel lengths. The model is described by a single drain current equation, valid for both weak and strong inversion regions of device operation. The model contains a new velocity-field (/spl upsi/-/spl epsi/) relation for carriers in the channel region. Combining this relation with the channel length modulation expression, obtained using engineering approximations to the two-dimensional fields near the drain end in saturation, results in an accurate drain conductance equation. The value for the carrier saturated velocity extracted from the I-V data for different CMOS technologies is 7-8/spl times/10/sup 6/ cm/s for electrons and 5-6/spl times/10/sup 6/ cm/s for holes, consistent with the reported values. The model not only predicts accurate output conductance, which is important for analog design, but also accurately simulates intrinsic gate capacitances for short channel devices. Since the model is inherently continuous, device conductances and capacitances are smooth and continuous at the transition points. This continuity results in enhanced convergence properties of the circuit simulator SPICE. Because the model is physically based, the temperature dependence of device characteristics in the temperature range 0-120/spl deg/C can easily be predicted simply by taking the temperature dependence of the threshold voltage, carrier mobility and velocity saturation parameters.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Analytical and experimental studies of thermal noise in MOSFET's

An analysis of the channel thermal noise in MOSFET's based on the one-dimensional charge sheet model, is presented. The analytical expression is valid in the strong, moderate, and weak inversion regions. The body effect on the device parameters relevant to the thermal noise is discussed. A measurement technique as well as experimental results of P- and N-MOSFET's of a 1.2 /spl mu/m radiation hard CMOS process are presented. The calculated channel thermal noise coefficient /spl gamma/ as in i/sub d//sup 2///spl Delta/f=4kT /spl gamma/ g/sub do/, agrees well with experimental data for effective device channel length as short as 1.7 /spl mu/m. >

Anomalous capacitance-voltage characteristics of BF2-implanted and rapid thermal annealed p+-polycrystalline silicon gate metal-oxide-semiconductor structures

Anomalous capacitance-voltage (C-V) characteristics of BF2-implanted p+-polycrystalline silicon (polysilicon) gate metal-oxide-semiconductor (MOS) structures annealed by rapid thermal annealing (RTA) are reported for the first time. It is found that both high-frequency and quasi-static C-V curves exhibit an increased capacitance at the depletion and weak inversion regions, which increases with p+-polysilicon RTA drive-in durations. The quasi-static C-V curves show a gate bias dependence of the inversion capacitance which shows a distorted ‘‘plateau’’ (i.e., reduced inversion capacitance for a very narrow gate voltage range) in the strong inversion regions. These anomalous C-V characteristics are believed to be due to the penetrated B-F complexes which act as interface state and deep level defect centers.

Value and gradient distribution of the quasi-Fermi level in MOS transistor channels

The distribution of the quasi-Fermi level along the channel is theoretically considered for the charge carriers in the weak and strong inversion regions as well as in the intermediate region. It is shown that the gradient of the quasi-Fermi level changes strongly along the channel if the drain voltage is more than kT/q. A numerical calculation is made for the concrete case of transistors with an oxide of thickness 50 Å. The experimentally measured distribution of the quasi-Fermi level is in good agreement with that of calculation. The measured value of the Hall voltage is found to be proportional to the gradient of the quasi-Fermi level in accordance with theoretical considerations. [Russian Text Ignored]

CdTe/Langmuir-film m.i.s. structures

Langmuir films based on cadmium stearate have been successfully deposited on to the surface of p-type CdTe. The measured C/V curves show, for the first time, the accumulation, depletion and weak-inversion regions typical of an ideal device. The G/V curves show a sharp peak in the depletion region at high frequencies which is thought to be due to losses at interface states. An initial estimate of the density yields an average value of 1011 states cm−2.

Electrical characteristics of the SiO 2Si interface near midgap and in weak inversion

The electrical characteristics of the SiO 2Si interface in depletion are well understood, but very little information is available on the behavior of surface states in the midgap and weak inversion regions. In this work we develop a general numerical model for the surface state branch which is valid in all bias regions. The model is compared to experimental results in detail, and the surface state density and electron capture cross-section are deduced in the lower half of the bandgap (weak inversion) for two thick oxide samples. The electron capture cross-section was found to be relatively independent of energy through midgap and into weak inversion, in contrast to the exponential dependence on energy reported by others in depletion. The ratio of electron capture cross-section to hole capture cross-section is measured at midgap and found to have a systematic dependence on midgap surface state density, independent of substrate orientation or sample annealing. It is possible that this observation arises because of inadequacies in the model.