Weak Inversion Region Research Articles

Improving power efficiency of a two-stage operational amplifier for biomedical applications

By using compensation technique with feed-forward path, an improved folded cascode operational transconductance amplifier (OTA) that operates in weak inversion region is designed. The proposed configuration consists of composite transistors, recycling structure and feed-forward compensation path. In comparison with the typical folded cascode CMOS Miller amplifier, this design has higher DC gain, unity gain frequency and slew rate without adversely affecting the noise and offset performance. The presented OTA is simulated in 0.18 μm CMOS technology and the simulation results confirm the theoretical analyses. Finally, the proposed amplifier has a 104.5 dB open-loop DC gain and 69.4 kHz unity gain frequency @ 0.6 V supply voltage while the power consumption is 300 nW.

Impact of Technology Scaling on ISFET Performance for Genetic Sequencing

This paper investigates the impact of technology scaling according to Moore’s law on the performance of ion-sensitive field-effect transistors (ISFETs) as pH sensors for genetic sequencing. Two commercial CMOS process families, including 0.35, 0.18, 0.13, and 0.09 $\mu $ m processing nodes, have been used to model ISFETs of different sizes and biasing conditions with simulation results indicating that the noise behavior of a ISFET deviates significantly from the underlying MOSFETs. In particular, a capacitive division effect is observed at the gate due to the passivation and parasitic capacitances, effectively attenuating any signal and noise. The dependence of the attenuation on gate parasitics means that smaller devices, which operate in the weak inversion region, cause the least attenuation, therefore, lowest input referred noise, a result that is contradictory to what is expected with MOSFETs.

Design of bandgap reference circuits in a 65 nm CMOS technology for HL-LHC applications

This work is concerned with the design and characterization of bandgap reference circuits capable of operating with a power supply of 1.2 V in view of applications to HL-LHC experiments. Due to the harsh environment foreseen for these devices, different solutions have been considered and implemented in a 65 nm CMOS technology. Together with a conventional structure which exploits bipolar devices, a smaller solution based on pn diodes and a version with MOS transistors biased in weak inversion region are included. This paper intends to describe and compare the features of the different circuits designed.

A CURRENT-MODE RMS-TO-DC CONVERTER BASED ON TRANSLINEAR PRINCIPLE

In this paper a low-power current-mode RMS-to-DC converter is proposed. The proposed converter includes absolute value circuit, squarer/divider circuit, low-pass filter and square root circuit which employ CMOS transistors operating in weak inversion region. The RMS-to-DC converter has low power consumption (<1μW), low supply voltage (0.9V), wide input range (from 50 nA to 500 nA), low relative error (<3 %), and low circuit complexity. Comparing the proposed circuit with two other current-mode circuits shows that the former outperforms the latters in terms of power dissipation, supply voltage, and complexity. Simulation results by HSPICE show high performance of the circuit and confirm the validity of the proposed design technique.

Low-voltage process-insensitive frequency compensation method for two-stage OTA with enhanced DC gain

A proposed low-voltage pseudo-cascode frequency compensation technique to improve the phase-margin of the two-stage OTA in weak-inversion region is introduced. Furthermore, a enhanced composite-transistor technique to increase the DC gain of the two-stage OTA in weak-inversion region is also presented in this paper. Both the proposed techniques achieve enhanced performance without requiring any additional power dissipation. To compare the performance advantages of the proposed techniques, two two-stage OTAs were designed in a UMC 0.18μm CMOS process. Simulation results show that the DC gain of the two-stage OTA with enhanced composite-transistor is increased by a factor of 17dB, the unity-gain bandwidth of the OTA with the proposed pseudo-cascode compensation technique improved 18%, the phase-margin of the OTA is increased by 33%, and it is maintained over a factor of 300 (from 5 to 1500nA) scaling in its bias current.

A 6.13 µW and 96 dB CMOS Exponential Generator

In this brief, a new low-voltage CMOS circuit to produce current-mode exponential characteristics is proposed. MOSFET transistors in weak-inversion region and translinear principle for the temperature cancellation were used. The functionality of the proposed design confirmed with 0.35 μm CMOS process technology using ±0.75 V supply voltage. Results demonstrate the theoretical analysis and verify the efficiency of the proposed structure compared with previously reported designs. Around 96 linear-in-dB output current range is achieved with ±0.5 dB linearity error over normalized input range from -5.75 to 5.75. The maximum deviation in the output current is ±1.27 and ±3.35 dB due to 100 °C temperature variations and ±10% supply voltage fluctuation, respectively.

Topological Insulator Bi2Se3 Nanowire Field Effect Transistors

Topological insulators (TI) have insulating band gaps in the bulk but gapless surface states topologically protected by time-reversal symmetry [1, 2]. Bi2Se3, a well-known semiconductor and thermoelectric material, is a TI with a bulk band gap of 0.35 eV and a single Dirac cone on the surface [2, 3]. Most current experimental research focus on the surface states of thin TI samples exfoliated from bulk material [4]. A few groups have reported modification of the surface conduction of such exfoliated TI samples by doping, applying a vertical electric field or polarized light. However, high-performance microelectronic devices based on topological insulators such as the analog of metal oxide semiconductor field effect transistors (MOSFETs) have not yet been reported.MOSFETs are the basic building blocks for digital and analog circuits. In this work, we fabricated and measured surrounding-gate Bi2Se3 nanowire (NW) field-effect transistors. The current-voltage (I-V) characteristics were measured at different temperatures, exhibiting excellent performance: well-saturated output I-V curves and large on/off ratio. The surface metallic conduction can be separated from the bulk conduction with gate electric field at different temperatures. We found that the surface conduction increases as temperature decreases, while the bulk conductance decreases with decreasing temperature. This indicates that the carriers at the surface and the carriers inside the bulk Bi2Se3 body have different properties. In addition, the Bi2Se3 FET exhibits I-V characteristics different to conventional MOSFETs in the weak inversion region. The drain current (IDS) increases significantly beyond 3фt (фt is thermal potential). This trend indicates that the Bi2Se3 nanowire FET current does not follow the same diffusion current model as that describes conventional MOSFETs. We believe IDSin the weak/moderate conductive regions is also dominated by drift current.To further study the topological insulator properties, we have performed magneto-transport measurements and observed Aharonov-Bohm (AB) oscillation that arise from the surface conduction channel that surrounds the Bi2Se3 NW in these FETs. The AB oscillations are obtained at low temperatures with a magnetic field oriented along the channel direction. The devices exhibit the anomalous AB effect [5] while maintaining high FET performance. The AB oscillations have a period of h/e and can be significantly tuned by the top surrounding gate. The resistance has a peak at B = 0 and decreases as the magnetic field increases. This phenomenon indicates that the surface states may be bound together by their spin in the circle and activated for conduction by the magnetic field along the axial direction of the circle.In summary, we have fabricated and measured Bi2Se3nanowire field effect transistors with excellent I-V characteristics. The devices exhibit anomalous AB oscillation, which may lead to new discovery of spin coupling in topological insulators.

A 60-dB Gain OTA Operating at 0.25-V Power Supply in 130-nm Digital CMOS Process

This paper presents a 60-dB gain bulk-driven Miller OTA operating at 0.25-V power supply in the 130-nm digital CMOS process. The amplifier operates in the weak-inversion region with input bulk-driven differential pair sporting positive feedback source degeneration for transconductance enhancement. In addition, the distributed layout configuration is used for all the transistors to mitigate the effect of halo implants for higher output impedance. Combining these two approaches, we experimentally demonstrate a high gain of over 60-dB with just 18-nW power consumption from 0.25-V power supply. The use of enhanced bulk-driven differential pair and distributed layout can help overcome some of the constraints imposed by nanometer CMOS process for high performance analog circuits in weak inversion region.

An accurate method for predicting temperature-dependent current mismatch in weak inversion region of long and wide channel MOSFET without subthreshold hump

We have found and verified that the current mismatch σ(ΔI/I) in the weak inversion region can be accurately predicted on the basis of the transconductance efficiency gm/I when a MOSFET does not have a subthreshold hump. We have also verified that, in a relatively long and wide channel MOSFET, the value of gate-voltage mismatch σ(ΔI/gm)(LW)1/2 in the weak inversion region converges to a constant value, regardless of the channel size and temperature. The constant value is determined by the MOSFET structure. In our method, both the convergence value of σ(ΔI/gm)(LW)1/2 in the weak inversion region and the gm/I behavior are used as input information of the σ(ΔI/I) prediction. It is possible to take this constant convergence value as an approximate value of σ(ΔI/gm)(LW)1/2, also in the moderate inversion region. Using this value, our method of σ(ΔI/I) prediction can be applied to the moderate inversion region with a reasonable degree of accuracy. In addition, a method for improving the accuracy of the predictions in the strong inversion region will be presented. We will discuss the mechanism that causes the value of σ(ΔI/gm)(LW)1/2 in the weak inversion region to become a constant value. On the other hand, when a MOSFET has a subthreshold hump, the constant value approximation of σ(ΔI/gm)(LW)1/2 in the weak inversion region cannot be used. The value of σ(ΔI/gm)(LW)1/2 in weak and moderate inversion regions increases with a decrease in current. This increase randomly fluctuates depending on the wafer or temperature. As a result, to predict the current mismatch σ(ΔI/I) accurately, it is necessary to remove the subthreshold hump of a MOSFET completely.

0.5 V sinh-domain differentiator

A differentiator topology realised by employing the concept of the filtering in the sinh-domain is introduced in this article. This is constructed from appropriately configured non-linear transconductor cells. The employment of MOS transistors operated in the weak inversion region offers the capability for ultra-low-voltage operation. Additional benefits are the electronic adjustment of the frequency characteristics and the inherent class-AB operation of the differentiator, originated from its sinh-domain nature. The performance of the differentiator has been evaluated and compared with that achieved by the corresponding already introduced log-domain topology.

Analysis of flicker and thermal noise in p-channel Underlap DG FinFET

In this paper, we analyze the flicker and thermal noise model for underlap p-channel DG FinFET in weak inversion region. During the analysis of current and charge model, minimum channel potential i.e. virtual source is considered. Initially, the drain current for both long and short channel of DG FinFET are evaluated and found to be well interpreted with experimental results. Further, the flicker and thermal noise spectral density are derived. The flicker noise power spectral density is compared with published experimental results, which shows a good agreement between proposed model and experimental result. During calculation we have considered variation of scattering parameter and furthermore, the degradation of effective mobility is taken into account for ultrathin body. The variation of structural parameters such as gate length (Lg), body thickness (tSi) and underlap length (Lun) are also considered. The degradation of gate noise voltage with frequency, underlap length and gate length signify that p-channel DG FinFET device can be a promising candidate for analog and RF applications.

A Novel 1.2–V 4.5-ppm/°C Curvature-Compensated CMOS Bandgap Reference

This paper proposes a novel CMOS bandgap reference (BGR) with high-order curvature-compensation by using MOS transistors operating in weak inversion region. The mechanism of the proposed curvature-compensation technique is analyzed thoroughly and the corresponding BGR circuit was implemented in standard CMOS 0.18 μm technology. The experimental results show that the proposed BGR achieves 4.5 ppm/°C over the temperature range of -40°C to 120°C at 1.2 V supply voltage. It consumes only 36 μA. In addition, it achieves line regulation performance of 0.054%/V. It is suitable for low-power applications requiring references with high precision.

Modeling CMOS Ring Oscillator Performance<newline/> as a Randomness Source

<?Pub Dtl=""?> In order to maximize randomness of CMOS Ring Oscillators (RO) used in Random Number Generators (RNG), possibility of weak inversion operation of CMOS transistors is investigated. To predict weak inversion noise performance of RO, phase noise and jitter models of a CMOS RO in weak inversion operating region are obtained. Differential Ring Oscillator (DRO) and Inverter-based Ring Oscillator (IbRO) cases are both investigated. For each case, the model covers the flicker and the white noise component of phase noise and jitter. The derived models are verified by measurement results. 0.25 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\mu$</tex></formula> m standard CMOS process has been used with a supply voltage of 0.7 V for DRO and 0.5 V for IbRO. Furthermore, phase noise and jitter behavior of a CMOS RO in strong and weak inversion region are compared through analytical models, simulations, and measurements. Even though white noise component of phase noise uses two different models for weak and strong inversion regions of operation, these two models exhibit continuity. Flicker noise component in weak inversion is much lower than the one in strong inversion, which also reduces the corner frequency. For a fair comparison of randomness performances, a randomness parameter is defined and randomness equations are derived for each case.

MOST Moderate–Weak-Inversion Region as the Optimum Design Zone for CMOS 2.4-GHz CS-LNAs

In this paper, the MOS transistor (MOST) moderate-inversion (MI)-weak-inversion (WI) region is shown to be the optimum design zone for CMOS 2.4-GHz common-source low-noise amplifiers (CS-LNAs) focused on low power consumption applications. This statement is supported by a systematic study where the MOST is analyzed in all-inversion regions using an exhaustive CS-LNA noise-figure (NF)-power-consumption optimization technique with power gain constraint. Effects of bias choke resistance and MOST capacitances are carefully included in the study to obtain more accurate results, especially for the MI-WI region. NF, power consumption, and gain versus the inversion region are described with design space maps, providing the designer with a deep insight of their tradeoffs. The Pareto-optimal design frontier obtained by calculation-showing the MI-WI region as the optimum design zone-is reverified by extensive electrical simulations of a high number of designs. Finally, one 90-nm 2.4-GHz CS-LNA Pareto optimal design is implemented. It achieves the best figure of merit considering under-milliwatt CS-LNAs published designs, consuming 684 μW, an NF of 4.36 dB, a power gain of 9.7 dB, and a third-order intermodulation intercept point of -4 dBm with load and source resistances of 50 Ω.

A Differential CMOS Common-Gate LNA Linearized by Cross-Coupled Post Distortion Technique

A linearized differential common-gate CMOS low noise amplifier is proposed. The linearity is improved by a cross-coupled post distortion technique, employing auxiliary PMOS transistors in weak inversion region to cancel the third-order nonlinear currents of common-gate LNA and impair the second-order nonlinear currents of that. The negative conductance characteristic of cross-coupled auxiliary PMOS transistors improves the gain while the resulted NF is little affected. Furthermore, noise contribution and linearity deterioration from the cascode stage is eliminated by an inductor resonating with the parasitic capacitance observed at the source net of the cascode transistor. The LNA implemented in a 0.18 μm CMOS technology demonstrates that IIP3 and gain have about 8.2 dB and 1.4 dB improvements in the designed frequency band, respectively. The noise figure of 3.4 dB is obtained with a power dissipation of 6.8 mW under a 1.8 V power supply.

6.8 mW 15 dBm IIP3 CMOS common‐gate LNA employing post‐linearisation technique

A linearised differential common-gate CMOS low-noise amplifier (LNA) is proposed. The linearity is improved by a cross-coupled post-distortion technique, employing PMOS in a weak inversion region as an auxiliary field effect transistor to cancel the third-order nonlinear currents of a common-gate LNA and impair the related second-order nonlinear currents. Meanwhile, the resulting noise figure is little affected. The LNA implemented in a 0.18 μm CMOS technology demonstrates that IIP3 and gain have about 8.2 and 1.5 dB improvements in the designed frequency band, respectively. A NF of 3.4 dB is obtained with a power dissipation of 6.8 mW under a 1.8 V power supply.

Designing high-value resistive network using weak inversion region of a PMOS device at the floating gate of a sensor

In this paper, we propose a design solution for implementing high-value resistance circuit, intended to bias the floating gate of PolyVinyliDene Fluorine (PVDF) based tactile sensors. The solution was proposed to design circuits based on Twin-tub and N-well processes. The formulations of mathematical equations were derived from EKV model. Our simulation results are in terms of frequency and transient responses, and they show that both the circuits were able to realize very high value of resistance suited for this sensor application in typical cases. However, in terms of process, voltage, and temperature variations, the results shown by the N-well process were better than those of the Twin-tub process at corner cases.

A CMOS current-mode log(x) and log(1/x) functions generator

A novel Complementary Metal Oxide Semiconductor (CMOS) current-mode low-voltage and low-power controllable logarithmic function circuit is presented. The proposed design utilises one Operational Transconductance Amplifier (OTA) and two PMOS transistors biased in weak inversion region. The proposed design provides high dynamic range, controllable amplitude, high accuracy and is insensitive to temperature variations. The circuit operates on a ±0.6 V power supply and consumes 0.3 μW. The functionality of the proposed circuit was verified using HSPICE with 0.35 μm 2P4M CMOS process technology.

An Ultra-Low Power V-Band Source-Driven Down-Conversion Mixer With Low-Loss and Broadband Asymmetrical Broadside-Coupled Balun in 90-nm CMOS Technology

This paper proposes a microwatt source-driven down-conversion mixer with broadband asymmetrical broadside-coupled baluns in a 90-nm CMOS low-power process. The forward body biased (FBB) technique reduces the threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> ) and supply voltage for operation in the near weak inversion region in millimeter-wave mixer designs. To effectively reduce the size of the chip, an asymmetrical broadside-coupled balun is developed with a bandwidth of 103 GHz (from 34 to 137 GHz) with a low insertion loss of 3.66 dB (3 dB for an ideal balun) at 58 GHz. The chip area of the balun is 0.016 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The proposed FBB mixer has a 4.2-dB peak conversion gain and a 14.3-dBm input third-order intercept point at 55 GHz under a 2-dBm local-oscillator power. The dc power of the FBB mixer core is only 139 W, while it draws a 278-μA dc current from a 0.5-V supply. The fabricated FBB mixer, comprising two asymmetrical broadside-coupled baluns, and all of test pads and dummy blocks, occupies an area of 0.72 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . An FoM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Mixer1</sub> that is obtained using the ultra-low power consumption FBB mixer is as high as 23.4.

A High linearity CMOS low noise amplifier for 3.66 GHz applications using current-reused topology

A narrow band CMOS low noise amplifier (LNA) achieving high third-order input intercept point (IIP3) is proposed exploiting a non-linearity cancelation technique at RF frequency. In the modified derivative superposition (MDS) technique, one transistor is biased in the strong inversion region and the other is biased in the moderate inversion region instead of weak inversion region. A current-reused technique is employed to increase the trans-conductance (gm) of the amplifier and as well as the gain of LNA without increasing the power consumption. The linear LNA was designed and simulated in 0.13μm CMOS process. A gain of 14dB at 3.66GHz was exhibited and the simulated noise figure (NF) was 2dB. An IIP3 of 10.5dBm and a power consumption of 2.4mW from a 0.8V supply voltage were achieved. An input return loss (S11) of −10.6dB and an output return loss (S22) of −27dB were provided.