Wavefront Arrays Research Articles

Dual-View Integral Imaging 3D Display Based on Multiplexed Lens-Array Holographic Optical Element

We propose a dual-view integral imaging 3D display based on a multiplexed lens-array holographic optical element (MHOE). A MHOE is a volume holographic optical element obtained by multiplexing technology, which can be used for dual-view integral imaging 3D display due to the angle selectivity of the volume HOE. In the fabrication of the MHOE, two spherical wavefront arrays with different incident angles are recorded using photopolymer material. In the reconstruction, two projectors are used to project the elemental image arrays (EIA) with corresponding angles for two viewing zones. We have developed a prototype of the dual-view integral imaging display. The experimental results demonstrate the correctness of the theory.

Transputer Implementation of the EKF-Based Learning Algorithm for Multilayered Neural Networks used in Classification of EEG Signals

Artificial neural network approaches for classification of EEG signals using the widely known back-propagation algorithm to train the network are reported in the literature. However, the speed of convergence of the backpropagation algorithm is rather slow. The Extended Kalman Filtering (EKF) based learning algorithm which has a much faster convergence speed is suggested for training the neural network used in classification of EEG signals.A further reduction in computation time is possible if paralle processing of the EKF based learning algorithm is introduced. Systolic and wavefront arrays have been suggested as suitable architectures for parallel processing. The transputer is one such architecture which has been specially desinged for use as a processing node in a parallel processing network. Transputer implementation of the EKF based learning algorithm for multilayered neural network used in classification of EEG signals is the subject matter of this paper.

Parallel implementation of radar tracking extended Kalman filters on transputer networks

The extended Kalman filter (EKF)used in radar tracking applications is computationally intensive leading to difficulties in broadband real-time applications. Hence, it is necessary to resort to parallel processing techniques. With the advent of very large scale integration (VLSI) technology, different types of architectures such as systolic arrays and wavefront arrays have been developed for this purpose. The transputer is one such architecture that can be used as a processing node in a parallel processing network. Therefore, two configurations, namely, pipe configuration and mesh configuration are developed for transputer implementation of radar tracking extended Kalman filtering. The EKF algorithm is analyzed in detail for reduction of number of computations. The transputer implementations are written using ANSI-C language with the proposed reduction of matrix operations and run using a mother board with 4 TRAMS each containing one T800 transputer. A typical maneuvering trajectory is simulated and used to compare the computation time per iteration of single and four transputer implementations of the tracking Kalman filter. Further, the speed-up comparison of sequential implementation of EKF, both with and without the proposed reduction of computations, is reported. >

Efficient technique for partitioning and programming linear algebra algorithms on concurrent VLSI architectures

An efficient technique for partitioning and programming linear algebra algorithms on concurrent architectures is described and applied to 2-D wavefront arrays. The mapping of the computational elements (processes) to processors is based on the concept of folding. The mapping pattern on the 2-D full-size mesh of processes is composition of symmetric tiles of size 2 square root (N)*2 square root (N), N being the number of processors. The algorithm can be partitioned according to a globally sequential, locally parallel scheme. The code optimisation is performed by programming a few different types of tile, according to the algorithm. When the size of the problem is much larger than the size of the mesh of processors, a linear speed-up is achieved independently of the number of processors. Experimental results are presented for matrix multiplication, LU decomposition and the solution of triangular system equations on 2-D meshes of transputers programmed in Occam.

Fast direct implementations of two‐dimensional digital filters via systolic and wavefront arrays

Fast direct implementations of two‐dimensional digital filters via systolic and wavefront arrays

Four state asynchronous architectures

An approach is presented to high-performance asynchronous architectures offering significant advantages over conventional clocked systems, without some of the drawbacks normally associated with asynchronous techniques. As the level of integration increases, an asynchronous wavefront array designed using the techniques described will have three important advantages over the equivalent synchronous systolic array: faster throughput (rate at which data are clocked through a system), reduced design complexity, and greater reliability. The benefits and drawbacks of using the asynchronous technique are highlighted using three wavefront arrays: two one-dimensional multipliers, and a two-dimensional sorter. All three can be built using just one basic building block.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Control generation in the design of processor arrays

The problem of mapping algorithms onto regular arrays has received great attention in the past. Results are available on the mapping of regular algorithms onto systolic or wavefront arrays. On the other hand, many algorithms that can be implemented on parallel architectures are not completely regular but are composed of a set of regular subalgorithms. Recently, a class of configurable processor arrays has been proposed that allows the efficient implementation of piecewise regular algorithms. In contrary to pure systolic of wavefront arrays they are distinguished by a dynamic configuration structure. The known trajectories, however, cannot be applied to the design of configurable processor arrays because the functions of the procesing elements and the interconnection structure are time- and space-dependent. In this paper, a systematic procedure is introduced that allows the efficient design of configurable processor arrays including the specification of the processing elements and the generation of control signals. Control signals are propagated through the processor array. The proposed design trajectory can be used for the design of regular arrays or configurable arrays.

Systolic array designs for Kalman filtering

Systolic Kalman filter (SKF) designs based on a triangular array (triarray) configuration are presented. A least squares formulation, which is an expanded matrix representation of the state space iteration, is adopted to develop an efficient iterative QR triangularization and consecutive data prewhitening formulations. This formulation has advantages in both numerical accuracy and processor utilization efficiency. Moreover, it leads naturally to pipelined architectures such as systolic or wavefront arrays. For an n state and m measurement dynamic system, the SKF triarray design uses n(n+3)/2 processors and requires only 4n+m timesteps to complete one iteration of prewhitened Kalman filtering system. This means a speedup factor of approximately n/sup 2//4 when compared with a sequential processor. Also proposed for the colored noise case are data prewhitening triarrays which offer compatible speedup performance for the preprocessing stage. Based on a comparison of several competing alternatives, the proposed array processor may be considered a most efficient systolic or wavefront design for Kalman filtering.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Block decomposition structures for the fast modular implementation of two-dimensional digital filters

A general structure is presented for the block realization of two-dimensional infinite impulse response digital filters, which is based on the two-dimensional matrix convolution equations and the decomposition of their associated transfer function matrices. The proposed decomposition may be considered as an extension of the scalar decomposition technique, which has already been used for the realization of two-dimensional digital filters associated with two-variable polynomials. The decomposition structure is considered in two different forms, which correspond to the direct forms I and II. It is shown that if a given two-dimensional single-input, single-output filter is realizable, then realizable block decomposition structures may be always selected. The proposed approach is general and applies without any restriction for the block implementation of any two-dimensional filter. The resulting structures are characterized by high inherent parallelism, modularity, regularity, reconfigurability, local interconnections, and very high sampling and throughput rates. Thus they are well suited for VLSI implementation and implementation via multiprocessor systems and array processors, such as systolic and wavefront arrays.

Performance analysis and optimization of VLSI dataflow arrays

Motivated primarily by their potential for VLSI implementation, wavefront arrays have recently attracted significant research interest. Relative to their systolic counterparts, the asynchronous, data-driven nature of wavefront arrays eliminates the need for global synchronization and control. However, performance analysis for wavefront arrays is more complex. In this paper we introduce a datallow graph model for the timing analysis of general (cyclic or acyclic), decision-free asynchronous architectures. We then show how the results of this analysis can be used to synthesize optimal (in terms of speed and storage) special-purpose hardware implementations of both general datallow arrays and regular wavefront arrays.

Experience with occam for simulating systolic and wavefront arrays

The use of occam as a simulation language for systolic and wavefront processor arrays is described. Partitioning problems which may arise are discussed and their implications for Transputer systems assessed. General principles for parallel simulation in occam are discussed, and occam is compared with other languages in this context.

On supercomputing with systolic/wavefront array processors

In many scientific and signal processing applications, there are increasing demands for large-volume and/or high-speed computations which call for not only high-speed computing hardware, but also for novel approaches in computer architecture and software techniques in future supercomputers. Tremendous progress has been made on several promising parallel architectures for scientific computations, including a variety of digital filters, fast Fourier transform (FFT) processors, data-flow processors, systolic arrays, and wavefront arrays. This paper describes these computing networks in terms of signal-flow graphs (SFG) or data-flow graphs (DFG), and proposes a methodology of converting SFG computing networks into synchronous systolic arrays or data-driven wavefront arrays. Both one- and two-dimensional arrays are discussed theoretically, as well as with illustrative examples. A wavefront-oriented programming language, which describes the (parallel) data flow in systolic/wavefront-type arrays, is presented. The structural property of parallel recursive algorithms points to the feasibility of a Hierarchical Iterative Flow-Graph Design (HIFD) of VLSI Array Processors. The proposed array processor architectures, we believe, will have significant impact on the development of future supercomputers.

VLSI design for massively parallel signal processors

In modern signal processing, there are increasing demands for large-volume and high-speed computations. At the same time, VLSI has had a noticeable effect on signal processing by offering almost unlimited computing hardware at low cost. These factors combined have affected markedly the rapid upgrading of current signal processors. We review the influence of the basic VLSI device technology and layout design on VLSI processor architectures. The array processors in which we take special interest are those for the common primitives needed in signal processing algorithms such as convolution, fast Fourier transforms and matrix operations. Regarding VLSI devices, special emphasis is placed on alleviating the burden of global interconnection and global synchronization. For cost-effective design, programmable processor modules are adopted. On the basis of these guidelines, we establish the algorithmic and architectural footing for the evolution of the design of VLSI array processors. We note that the systolic and wavefront arrays elegantly avoid global interconnection by effectively managing local data movements. Moreover, the asynchronous data-driven nature of the wavefront array offers a natural solution to get around the global synchronization problem. The wavefront notion lends itself to a wavefront language (matrix dataflow language (MDFL)) which simplifies the description of parallel algorithms.