Wave Dynamic Differential Logic Research Articles

Aging Effects on Template Attacks Launched on Dual-Rail Protected Chips

Profiling side-channel attacks in which an adversary creates a “profile” of a sensitive device and uses such profile to model a target device with similar implementation has received the lion’s share of attention in the recent years. In particular, template attacks are known to be the most powerful profiling side-channel attacks from an information theoretic point of view. When launching such attack, the adversary first builds a model based on the leakage of the profiling (training) device in his disposal which is then exploited in the second phase of the attack (i.e., matching) to extract the key from the target device. Discrepancies between the device used for modeling and the target device affect the attack success. The effect of process variation and temperature misalignment between the profiling and target devices in the template attack’s success has been studied extensively in literature, while the impact of device aging on the template attack’s success is yet to be investigated thoroughly. This paper moves one step forward and studies the impact of device aging, mainly Bias temperature Instability (BTI) and Hot Carrier Injection (HCI), in the devices that have been protected against power analysis attacks via dual rail logics. In particular, we focus on the Wave Dynamic Differential Logic (WDDL) circuits, and via extensive transistor-level simulations we will show how device aging misalignments between the profiling and target devices can hinder template attacks for both unprotected and WDDL protected counterparts. We mounted several attacks on the PRESENT cipher, with and without WDDL protection, at different temperatures and aging times. Our results shows that the attack is more difficult if there is an aging-duration mismatch between the training and target devices, and the attack-efficiency decrease is especially significant for mismatches of few weeks.

Invariant of Enhanced AES Algorithm Implementations Against Power Analysis Attacks

The security of Internet of Things (IoT) is a challenging task for researchers due to plethora of IoT networks. Side Channel Attacks (SCA) are one of the major concerns. The prime objective of SCA is to acquire the information by observing the power consumption, electromagnetic (EM) field, timing analysis, and acoustics of the device. Later, the attackers perform statistical functions to recover the key. Advanced Encryption Standard (AES) algorithm has proved to be a good security solution for constrained IoT devices. This paper implements a simulation model which is used to modify the AES algorithm using logical masking properties. This invariant of the AES algorithm hides the array of bits during substitution byte transformation of AES. This model is used against SCA and particularly Power Analysis Attacks (PAAs). Simulation model is designed on MATLAB simulator. Results will give better solution by hiding power profiles of the IoT devices against PAAs. In future, the lightweight AES algorithm with false key mechanisms and power reduction techniques such as wave dynamic differential logic (WDDL) will be used to safeguard IoT devices against side channel attacks by using Arduino and field programmable gate array (FPGA).

Design and Evaluation of Fluctuating Power Logic to Mitigate Power Analysis at the Cell Level

In this article, we design a novel cell-level power-analysis countermeasure, named fluctuating power logic (FPL), which diffuses the correlation between the real power consumption and the fixed data transitions by employing a <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">cascade voltage logic</i> . The countermeasure further acts as a cell-level <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{DD}$ </tex-math></inline-formula> randomizer, making it a strong candidate for implementing algorithmic countermeasure and exploiting its noise generation capabilities. This proposed scheme is illustrated by a standard flip-flop (FF). HSPICE-based simulation results show that the modified FF is resistant against power analysis (PA) at the cost of doubled power dissipation. Two illustrative case studies of PRESENT and AES substitutions have been explored. Furthermore, our proposal can be combined with other cell-level countermeasures against PA, such as wave dynamic differential logic. The resistance is evaluated by the correlation PA and the test vector leakage assessment. The new logic outperforms other counterparts in consideration of both security and cost, which renders it as a practical solution for resource-constrained systems. The proposed cell-level countermeasure can naturally mitigate other side-channel analysis such as electromagnetic analysis.

Leveraging Balanced Logic Gates as Strong PUFs for Securing IoT Against Malicious Attacks

A wave dynamic differential logic (WDDL)-based advanced encryption standard (AES) cryptographic circuit is explored as a strong physical unclonable function (PUF) primitive by exploiting the random load capacitance mismatches in WDDL gates induced by the fabrication process. As compared to the regular CMOS logic gates, the WDDL gates enhance the entropy of the proposed WDDL-based AES strong PUF significantly against power attacks. Furthermore, a non-linear product function is applied into the WDDL-based AES strong PUF to generate a high degree of the non-linearity between the input challenges and the output responses against machine-learning attacks. As demonstrated in results, the proposed WDDL-based AES strong PUF primitive achieves an approximately 50.7% inter-hamming distance (HD) and 97.7% reliability with a less than 25% loss ratio of input power entropy after power attacks and a large linear matching error (1032%) against machine-learning attacks.

VLSI Design flow for Secure Integrated Circuits based on DES, TDES, AES and Blowfish Algorithms and their performance

Information Communication Technology (ICT) and Information Security (IS) are playing vital role in the present day communications. Information is prone to side channel attacks at software level where as it is very difficult to hack the information at hardware level. Security is the major concern in the paperless communication and cashless online transactions. This paper aims to implement the most secured Improved Modified Blowfish Algorithm (IMBFA) by incorporating cell substitution using Wave Dynamic Differential Logic (WDDL) and interconnect decomposition in the VLSI Design flow to not to allow the hacker to estimate or predict the key. Proposed IMBFA which can result in high speed, high throughput and effective memory utilization compared to Data Encryption Standard (DES), Triple Data Encryption Standard (TDES), Advanced Encryption Standard (AES) and Blowfish (BF). In this research paper, IMBFA yielded minimum delay as 71.067 ns, frequency of the design as 14.07 MHz, memory utilization as 62.481MB and throughput is 900Mbps compared to AES, TDES and DES algorithms. It is simulated using ModelSim, Synthesized using Leonardo Spectrum and implemented using Verilog HDL.

A Lightweight Masked AES Implementation for Securing IoT Against CPA Attacks

A false key-based advanced encryption standard (AES) technique is proposed to prevent the stored secret key leaking from the substitution-box under correlation power analysis (CPA) attacks without significant power and area overhead. Wave dynamic differential logic (WDDL)-based XOR gates are utilized during the reconstruction stage to hide the intermediate data that may be highly correlated with the false key. After applying the false key and designing the reconstruction stage with the WDDL, the minimum measurement-to-disclose value for the proposed lightweight masked AES engine implementation becomes over 150 million against CPA attacks. As compared to an unprotected AES engine, the power, area, and performance overhead of the proposed AES implementation is negligible.

Predominance of Blowfish Over Triple Data Encryption Standard Symmetric Key Algorithm for Secure Integrated Circuits Using Verilog HDL

Computer data communication is the order of the day with Information Communication Technology (ICT) playing major role in everyone’s life, communicating with smart phones, tabs, laptops and desktops using internet. Security of the data transferred over the computer networks is most important as for as an organization is concerned. Hackers attempt hard to crack the software key and indulge in cyber crimes. In this paper, the main concern is not only to provide security to the data transferred at the software level but it provides the security at hardware level by the modified Blowfish Encryption and Decryption Algorithms. It results minimum delay, high speed, high throughput] and effective memory utilization compared to Blowfish (BF) and Triple Data Encryption Standard (TDES) algorithms. The implementation of Blowfish with modulo adder and Wave Dynamic Differential Logic (WDDL) is to provide security against Differential power analysis (DPA). In the proposed four implementations, BF with constant delay n-bit adder (BFCDNBA) yielded minimum delay, maximum frequency, high memory utilization and high throughput compared to BF with modulo adder and WDDL logic (BFMAWDDL), BF with modulo adder (BFMA) and TDES algorithms. The VLSI implementation of Blowfish and TDES algorithms is done using Verilog HDL.

A Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation

In this paper, we present an efficient countermeasure against fault sensitivity analysis (FSA) based on configurable delay blocks (CDBs). FSA is a new type of fault attack, which exploits the relationship between fault sensitivity (FS) and secret information. Previous studies reported that it could break cryptographic modules equipped with conventional countermeasures against differential fault analysis (DFA), such as redundancy calculation, masked and–or, and wave dynamic differential logic. The proposed countermeasure can thwart both DFA and FSA attacks based on setup time violation faults. The proposed ideas are to use a CDB as a time base for detection and to combine the technique with Li’s countermeasure concept that removes the dependency between FSs and secret data. The postmanufacture configuration of the CDBs allows minimization of the overhead in operating frequency that comes from manufacture variability. In this paper, we also present an implementation of the proposed countermeasure in application-specified integrated circuit, and describe its configuration method. We then investigate the hardware overhead of the proposed countermeasure for an advanced encryption standard processor and demonstrate its validity through an experiment.

Intra-Masking Dual-Rail Memory on LUT Implementation for SCA-Resistant AES on FPGA

In current countermeasure design trends against differential power analysis (DPA), security at gate level is required in addition to the security algorithm. Several dual-rail pre-charge logics (DPL) have been proposed to achieve this goal. Designs using ASIC can attain this goal owing to its backend design restrictions on placement and routing. However, implementing these designs on field programmable gate arrays (FPGA) without information leakage is still a problem because of the difficulty involved in the restrictions on placement and routing on FPGA. This article describes our novel masked dual-rail pre-charged memory approach, called “intra-masking dual-rail memory (IMDRM) on LUT”, and its implementation on FPGA for Side-Channel Attack-resistant (SCA-resistant) AES. In the proposed design, all unsafe nodes, such as unmasking and masking, and parts of dual-rail memory with unsafe buses (buses that are not masked) are packed into a single LUT. This makes them balanced and independent of the placement and routing tools. Inputs and outputs of all LUTs are masked, and so can be considered safe signals. Several LUTs can be combined to create a safe SBox. The design is independent of the cryptographic algorithm, and hence, it can be applied to available cryptographic standards such as DES or AES as well as future standards. It requires no special placement or route constraints in its implementation. A correlation power analysis (CPA) attack on 1,000,000 traces of AES implementation on FPGA showed that the secret information is well protected against first-order side-channel attacks. Even though the number of LUTs used for memory in this implementation is seven times greater than that of the conventional unprotected single-rail memory table-lookup AES and three times greater than the implementation based on a composite field, it requires a smaller number of LUTs than all other advanced SCA-resistant implementations such as the wave dynamic differential logic, masked dual-rail pre-charge logic, and threshold.

Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA

The wave dynamic differential logic (WDDL) has been identified as a promising countermeasure to increase the robustness of cryptographic devices against differential power attacks (DPA). However, to guarantee the effectiveness of WDDL technique, the routing in both the direct and complementary paths must be balanced. This paper tackles the problem of unbalance of dual-railsignals in WDDL design. We describe placement techniques suitable for tree-based and mesh-based FPGAs and quantify the gain they confer. Then, we introduce a timing-balance-driven routing algorithm which is architecture independent. Our placement and routing techniques proved to be very promising. In fact, they achieve a gain of 95%, 93%, and 85% in delay balance in tree-based, simple mesh, and cluster-based mesh architectures, respectively. To reduce further the switch and delay unbalance in Mesh architecture, we propose a differential pair routing algorithm that is specific to cluster-based mesh architecture. It achieves perfectly balanced routed signals in terms of wire length and switch number.

Designing Power Analysis Resistant and High Performance Block Cipher Coprocessor using WDDL and Wave-Pipelining

Novel design method and design flow of block cipher is presented based on the WDDL(Wave Dynamic Differential Logic)and Wave-Pipelining techniques.This design flow utilized the current commercially available EDA tools to a large degree.The WDDL and wave-pipelining based coprocessor not only resists power analysis,but also achieves high performance and low power consumption in nature.According to the design flow,this paper implements a DES coprocessor.The simulation results show that the novel design method achieves high performance,low power consumption and power analysis resistant ability at the cost of chip area.

Path switching: a technique to tolerate dual rail routing imbalances

Dual Rail Precharge (DRP) circuits, which are theoretically secure against differential power analysis attacks, suffer from an implementation problem: balancing the routing capacitance of differential signals. To solve this, four proposals have been put forward: Divided Wave Dynamic Differential Logic (DWDDL) (Tiri and Verbauwhede in DATE '04, pp. 246---251, [2004]), FatWire (Tiri and Verbauwhede in Cardis 2004, pp. 143---158, [2004]), Backend Duplication (Guilley et al. in Lecture Notes in Computer Science, vol. 3659, pp. 383---397, [2005]) and Three Phase Dual Rail (Bucci et al. in Lecture Notes in Computer Science, vol. 4249, pp. 232---241, [2006]). Of these, three (DWDDL, FatWire, Backend Duplication) proposals alter the routing mechanism of Standard Place and Route tools, which in turn introduces an additional step. The other proposal introduces a third phase which reduces the system's performance. In this paper we propose a new countermeasure, Path Switching, to address the routing problem in DRP circuits. From SPICE simulations we show that our proposal does not reveal the secret key for up to 300,000 traces, an increase of 75 times over normal Dual Rail circuits and 3000 times over normal single rail circuits.

An Analysis of Leakage Factors for Dual-Rail Pre-Charge Logic Style

In recent years, certain countermeasures against differential power analysis (DPA) at the logic level have been proposed. Recently, Popp and Mangard proposed a new countermeasure-masked dual-rail pre-charge logic (MDPL); this countermeasure combines dual-rail circuits with random masking to improve the wave dynamic differential logic (WDDL). They claimed that it could implement secure circuits using a standard CMOS cell library without special constraints for the place-and-route method because the difference between the loading capacitances of all the pairs of complementary logic gates in MDPL can be compensated for by the random masking. In this paper, we particularly focus on the signal transition of MDPL gates and evaluate the DPA-resistance of MDPL in detail. Our evaluation results reveal that when the input signals have different delay times, leakage occurs in the MDPL as well as WDDL gates, even if MDPL is effective in reducing the leakage caused by the difference in loading capacitances. Furthermore, in order to validate our evaluation, we demonstrate a problem with different input signal delays by conducting measurements for an FPGA.

AES-Based Security Coprocessor IC in 0.18-&amp;lt;tex&amp;gt;$muhbox m$&amp;lt;/tex&amp;gt;CMOS With Resistance to Differential Power Analysis Side-Channel Attacks

Security ICs are vulnerable to side-channel attacks (SCAs) that find the secret key by monitoring the power consumption or other information that is leaked by the switching behavior of digital CMOS gates. This paper describes a side-channel attack resistant coprocessor IC fabricated in 0.18- <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$muhbox m$</tex> CMOS consisting of an Advanced Encryption Standard (AES) based cryptographic engine, a fingerprint-matching engine, template storage, and an interface unit. Two functionally identical coprocessors have been fabricated on the same die. The first coprocessor was implemented using standard cells and regular routing techniques. The second coprocessor was implemented using a logic style called wave dynamic differential logic (WDDL) and a layout technique called differential routing to combat the differential power analysis (DPA) side-channel attack. Measurement-based experimental results show that a DPA attack on the insecure coprocessor requires only 8000 encryptions to disclose the entire 128-bit secret key. The same attack on the secure coprocessor does not disclose the entire secret key even after 1 500 000 encryptions.