Designing Power Analysis Resistant and High Performance Block Cipher Coprocessor using WDDL and Wave-Pipelining

Abstract

Novel design method and design flow of block cipher is presented based on the WDDL(Wave Dynamic Differential Logic)and Wave-Pipelining techniques.This design flow utilized the current commercially available EDA tools to a large degree.The WDDL and wave-pipelining based coprocessor not only resists power analysis,but also achieves high performance and low power consumption in nature.According to the design flow,this paper implements a DES coprocessor.The simulation results show that the novel design method achieves high performance,low power consumption and power analysis resistant ability at the cost of chip area.