Wafer Uniformity Research Articles

Numerical simulation and structural optimization of the diffusion furnace for crystal silicon solar cells

The diffusion furnace is an important device for crystalline silicon solar cell production. Given the rapid evolution of solar cell technology, large-scale, high-efficiency and mass-produced diffusion furnaces are required by the market. This puts forward higher requirements for the diffusion furnaces. In this study, a large-scale 3D model is established and validated by measured data in practical diffusion furnace. Its internal temperature, velocity and gas concentration fields are analyzed. The silicon wafer temperatures are found to be high at the top but low at the bottom. The temperature uniformity at both ends of silicon wafer groups is poor. To solve these problems, three structural optimization methods, namely the inlet pipe optimization, adding uniform-flow plates and the quartz boat optimization, are proposed and analyzed. The average mass fraction in the diffusion furnace is improved by 6.311% using the two-tube forked intake pipe. The uniform flow plates with evenly distributed pores on the lower half effectively improve the gas concentration uniformity on silicon wafer surfaces. The optimized quartz boat can improve the temperature uniformity of silicon wafers, though its deformation slightly increases by 0.338%. The silicon wafer temperature differences after quartz boat optimization are 13.77–50.27% smaller than those before optimization, which are conducive to reducing the thermal stress, the risk of thermal damage and the failure during manufacture and utilization of silicon wafers. Results in this study give guidelines for design and utilization of crystal silicon solar cell diffusion furnaces, some of which have been successfully used in Trina Solar Energy Co., China.

Optimization of surface filtration to enhance wafer uniformity by removing large particle in ceria slurry

Owing to the limitations of scaling down, the development of complex structures for chip design is progressing in the semiconductor industry. As a result, the chemical mechanical polishing (CMP) process has become essential for the precise control of micro-level steps and for maintaining surface uniformity between layers during the stacking process. Structural management and improved performance of the consumables used in CMP processes are required. In particular, controlling the abrasive particles in the slurry that directly contact the wafer surface is crucial. Large particles within the slurry can occur scratches and cause non-uniformity in the polishing process, thus the particle size distribution of the slurry must be regulated. In this study, two types of filtration systems were constructed to determine the optimal conditions for CMP of ceria slurry. Depth filtration effectively removes particles through a cake layer formation mechanism but has limitations in achieving a consistent pore size within the fiber layer. Consequently, separation efficiency for particle sizes is relatively low. In contrast, surface filtration consisting of a single membrane demonstrates a consistent correlation between pore size and the size of the filtered particles, resulting in high particle removal efficiency. The pore size capable of removing large particles without active particle loss was 200 nm. After evaluating slurry productivity and filter-induced agglomeration, 0.8 L per minute (LPM) was identified as the optimal flow rate. Additionally, after filtration at 0.8 LPM, the maximum reduction in removal rates was relatively small at 272.54 Å/min due to decreased edge removal rates. However, by removing large particles to implement a monodisperse state, an improvement in uniformity of 17.11 % was achieved. Therefore, the CMP performance can be enhanced using surface filtration to control the particle size distribution (PSD).

High-Quality 4H-SiC Homogeneous Epitaxy via Homemade Horizontal Hot-Wall Reactor

In this paper, using a self-developed silicon carbide epitaxial reactor, we obtained high-quality 6-inch epitaxial wafers with doping concentration uniformity less than 2%, thickness uniformity less than 1% and roughness less than 0.2 nm on domestic substrates, which meets the application requirements of high-quality Schottky Barrier Diode (SBD) and Metal–Oxide–Semiconductor Field-Effect Transistor (MOSFET) devices. We found that increasing the carrier gas flow rate can minimize source gas depletion and optimize the doping uniformity of the 6-inch epitaxial wafer from over 5% to less than 2%. Moreover, reducing the C/Si ratio significantly can suppress the “two-dimensional nucleation growth mode” and improve the wafer surface roughness Ra from 1.82 nm to 0.16 nm.

Spacer Side-wall Processed 0.15 μm GaN HEMT for Ka-band Application

In this paper, we have effectively demonstrated 150 nm-gate-length AlGaN/GaN high electron mobility transistors (HEMTs) on 4-inch SiC substrate. The 150 nm gate-length was accomplished by utilizing traditional I-line stepper photolithography, together with a nitride spacer side-wall. This method offers superior processing efficiency compared to E-beam lithography with high wafer uniformity. The devices processed with this spacer side-wall aided method demonstrated comparable electrical performances as that of E-beam processed one with fT of 45 GHz, fMAX of 80 GHz, Pout of 31 dBm and PAE of 45% at 29 GHz, which can be imported to large scale manufacturing.

Influence of Carbon Source on the Buffer Layer for 4H-SiC Homoepitaxial Growth.

In this study, we systematically explore the impact of C/Si ratio, pre-carbonization time, H2 etching time, and growth pressure on the buffer layer and subsequent epitaxial layer of 6-inch 4H-SiC wafers. Our findings indicate that the buffer layer's C/Si ratio and growth pressure significantly influence the overall quality of the epitaxial wafer. Specifically, an optimal C/Si ratio of 0.5 and a growth pressure of 70 Torr yield higher-quality epitaxial layers. Additionally, the pre-carbonization time and H2 etching time primarily affect the uniformity and surface quality of the epitaxial wafer, with a pre-carbonization time of 3 s and an H2 etching time of 3 min found to enhance the surface quality of the epitaxial layer.

High-performance uniform stepper-based InP double-heterojunction bipolar transistor (DHBT) on a 3-inch InP substrate

In this paper, InP Double-Heterojunction Bipolar Transistors (DHBTs) on a 3-inch InP substrate is demonstrated through stepper-based photolithography. The performance of the fabricated InP DHBTs such as DC characteristics, high-frequency characteristics, and uniformity of the 3-inch wafer is investigated to verify the stepper-based fabrication process. To improve the high-frequency characteristics, the self-aligned base-emitter contact is realized by using the high height-to-width ratio and vertical sidewall emitter profile of the Au electroplating process. The fabricated DHBTs with WE = 0.6 μm and LE = 15 μm exhibits current gain (β) = 50 at VCE = 1.0 V and an open-base common-emitter breakdown voltage (BVCEO) of 5.7 V at JC = 0.01 mA/µm2 and 7.5 V at JC = 0.1 mA/µm2, respectively. Moreover, the fabricated DHBTs with WE = 0.6 μm and LE = 15 μm show excellent fT of 244 GHz and fmax of 221 GHz at JC = 4.4 mA/μm2 and VCE = 1.6 V. In order to evaluate the uniformity of the fabricated DHBTs, we measure current gain (β) and high-frequency characteristics with WE = 0.6 μm and LE = 15 μm and the average values and standard deviation of the β, fT, and fmax are β = 49.3 ± 1.9, fT = 241.4 ± 3.8 GHz, and fmax = 221.5 ± 4.0 GHz, respectively. Thanks to the optimized stepper-based fabrication process, the fabricated InP DHBTs exhibit well-balanced high-frequency characteristics and excellent uniformity.

Study on the 12 in. wafer uniformity of high aspect ratio TSV filling by using rotation cathode

In 2.5/3D(2.5/3-dimensional) packages, TSV (Through-Silicon Via) technology is crucial for achieving high performance and low power consumption. However, there are still challenges when it comes to uniformly filling TSVs on 300 mm whole wafers without defects. This study focuses on addressing this issue by designing a rotating cathode carrier with a 300 mm diameter, simulating the plating environment in different areas of a 300 mm wafer. The effects of plating conditions, such as cathode rotational speed and chip mounting position, on the filling of TSV are investigated. The TSV have a hole diameter of 10 μm and a depth of 100 μm.The findings reveal that when the cathode carrier rotates at a speed of 30 rpm, different areas of the analog wafer exhibit complete filling of TSV. Additionally, a surface plating layer with an average thickness of approximately 3 μm is obtained.

SiGe Selective Etching to Enable Bottom and Middle Dielectric Isolations for Advanced Gate-All-Around FET Architecture

Formulated chemical ACT® SG6xxx series demonstrated SiGe etching selective to SiGe with lower Ge concentration. SiGe etching rate on SiGe/Si multi-stack shown steep trend as a function of Ge concentration, resulting in 338 of selectivity between SiGe30% and SiGe15%. Also, apparent loss on SiN and SiO2 was not observed. Moreover, SiGe etch rate was not impacted by chemical flow in the beaker. It suggests reaction-controlled based etching, which leads to good within wafer uniformity in etching rate of 300mm wafer spin processing. In conclusion, ACT® SG6xxx series is a promising option for the formation of BDI/MDIs in Nanosheet, Forksheet and CFET.

Heat-transfer modeling of the gas gap under a wafer

The wafer temperature is a critical observable in semiconductor manufacturing. One of the various mechanisms determining this temperature is the heat transfer in a gas gap between the wafer and the electrostatic chuck (ESC). Various correlations for this heat transfer are available. However, to calculate more accurately the spatial distribution of this temperature, computing the flow in this gap is necessary. With this motivation in mind, this paper presents a computational fluid dynamics model (CFD) for the flow in the wafer-ESC gap that is designed to be easy to implement in industrial CFD codes. This model is tested in various channel-flow problems and then applied to a generic wafer-ESC configuration. For this configuration, CFD results show that varying the flow rate split between three zones, or the total flow rate, or the rugosity of the wafer affect the heat transfer coefficient and its spatial variation. This is important since controlling this variation would allow to maintain a uniform wafer temperature. The model could be used in more realistic wafer-ESC configurations to consider many other parameter variations, such as the size of injection holes, a radially varying gap distance, or the use of many injection zones. From a broader viewpoint, the model is applicable to vacuum problems other than the wafer-ESC configuration.

Design of Wafer Level Solder Seals – A Surface Energy Perspective

Wafer level vacuum packaging of quartz resonators and microelectromechanical system (MEMS) inertial sensors and RF switches have been successfully demonstrated by a number of investigators. The majority of these devices were sealed using reflow of gold-tin solder because of its superior hermeticity and benign processing conditions as compared to seals made using glass frit or anodic bonding. These successes have motivated efforts to integrate multiple sensors and active silicon devices within the same package to achieve improved performance and further reduce system size and cost. Sealing these large, heterogeneous assemblies at wafer level presents a more challenging problem than sealing small individual sensors, primarily due to wafer bow and irregularities in the seal surfaces. Wafer bow has been addressed in sealing wafers of individual sensors by plating metal stops adjacent to the seal rings, which allow the wafers to be pressed together to flatten the seal areas during bonding. This strategy cannot always be applied to sealing system devices because the amount of wafer bow is greater than that associated with more uniform wafers of sensors and the larger area of system devices increase the residual stress on the solder seal. An alternative approach to pressing wafers flat throughout the bond process would be to relax the force during reflow and allow the solder to bridge the nonplanar interface. We have used analytical and numerical calculations to investigate the interplay between seal width, height and shape of the seal gap, and solder volume associated with this bonding strategy. A set of soldering experiments were conducted on test articles that allowed us to independently vary these parameters to evaluate our model predictions.

Noninvasive Photodelamination of van der Waals Semiconductors for High-Performance Electronics.

Atomically thin 2D van der Waals semiconductors are promising candidate materials for post-silicon electronics. However, it remains challenging to attain completely uniform monolayer semiconductor wafers free of over-grown islands. Here, the observation of the energy-funneling effect and ambient photodelamination phenomenon in inhomogeneous few-layer WS2 flakes under low-illumination fluencies down to several nW µm-2 and its potential as a noninvasive atomic-layer etching strategy for selectively stripping the local excessive overlying islands are reported. Photoluminescent tracking on the photoetching traces reveals relatively fast etching rates of around 0.3-0.8µm min-1 at varied temperatures and an activation energy of 1.7eV. By using crystallographic and electronic characterization, the noninvasive nature of the low-power photodelamination and the highly preserved lattice quality are also confirmed in the as-etched monolayer products, featuring a comparable density of atomic defects (≈4.2 × 1013 cm-2 ) to pristine flakes and a high electron mobility of up to 80 cm2 V-1 s-1 at room temperature. This approach opens a noninvasive postetching route for thickness uniformity management in 2D van der Waals semiconductor wafers for electronic applications.

Uniformity improvement of thickness and net donor concentration in halide vapor phase epitaxial β-Ga2O3 wafers prepared on miscut angle substrates

High uniformity of the thickness and net donor concentrations (N d-N a) in 100 mm diameter β-Ga2O3 (001) epitaxial wafer prepared by halide vapor phase epitaxy was demonstrated. An epitaxial wafer grown on a substrate with a miscut angle near 0° generated a specific epitaxial region with a lower growth rate and a higher N d-N a than the rest of the region, which deteriorated the wafer uniformity. In contrast, epitaxial wafers prepared on substrates with a miscut angle of –0.1° suppressed the occurrence of the specific epitaxial region, and an average thickness after chemical mechanical polishing of 10.6 μm with 5% tolerance and an average N d-N a without intentionally doping of 1.1 × 1016 cm−3 within 7% tolerance were successfully obtained.

Phase transformation pre-treatment of diamond wire-sawn multi-crystalline silicon wafers for metal-assisted chemical etching of solar cells

Phase transformation by the heat treatment, prior to metal-assisted chemical etching (MACE) of solar cells, has been proposed and studied, as a pre-treatment approach for diamond wire sawn (DWS) Si wafers. The results of the study show that the phase transformation pre-treatment can modify the microstructure of amorphous Si surface layers of DWS multi-crystalline (mc) Si wafers. The modified surface layer proved to be more reactive to the chemical etching solution, which was the primary factor for the improvement in the treated solar cells. A significant improvement on the surface uniformity and morphology of the textured Si wafer was achieved, subsequent to the pre-treatment, during the MACE texturization process. These solar cells based on the treated DWS mc-Si wafers displayed a gain of about 0.18% (absolute value), in the overall photoelectric conversion efficiency (η), when compared to the solar cells of the same batch, for the untreated wafers, on the same production line. It is hence, proven that this pre-treatment method, when used as a supplementary technique to the wet-chemical texturization process, has great potential as an effective application technology for solar cells based on DWS mc-Si wafers.

Uniformity and volume-representativity of consecutive submillimetre wafers of shale for SANS and USANS investigations

(Ultra) Small Angle Neutron Scattering (SANS/USANS) is a non-destructive technique suitable for characterization of porous structures from nano- to micro-pore size (1 nm to 20 μm), which has been widely used to characterize accessible and inaccessible porosity in tight unconventional hydrocarbon reservoirs (e.g., shales). In this study, SANS and USANS are used to examine the degree of nano- to micropore uniformity of the rock body on sub-millimetre to centimetre scale. This study presents a test of the hypothesis of volume representativity of pore structure information measured by SANS and USANS for shale wafers (0.22–1 mm) cut from six North American unconventional shale cores of different maturities (New Albany Shale and Marcellus Shale). Experimental reproducibility of USANS is further investigated for two wafers measured using various acquisition times. All samples show that fluctuations of the relative intensity generally decrease from the USANS Q-range (pore size from around 200 nm to 20 μm) to most of the SANS Q-range (pore size from around 5 nm to 700 nm), and peaks in the SANS large-Q region (for pores smaller than about 5 nm). There is a positive correlation between the spatial fluctuation of the relative SANS intensity and the scattering power of shales. In addition, the scattering intensity and its fluctuations is larger for the less mature shale cores. Shale is known to be highly heterogenous and the hypothesis of uniformity does not apply at sub-millimetre scale even for samples that appear homogeneous at visual inspection. This study presents an approach to minimise the variation through sample selection, data interpretation methodology and instrumental reproducibility tests. The best values of the microstructural spatial uniformity for the apparently homogeneous sections of a core (i.e., the SANS and USANS intensity variation) is less than ±10%.

Void Suppression in Glass Frit Bonding Via Three-Step Annealing Process.

In this work, void formation was systematically observed for the glass frit bonding technique as a function of the annealing temperature, annealing time, and annealing ambient. High annealing temperature and long annealing time were adopted to reach the maximum heat flux to avoid voids/bubbles. As demonstrated in the experiments, the voids appearing during glass frit bonding are related to the quantity of byproducts from the combustion of organic matter. The experimental results indicate that solely in air, under vacuum, or annealed for short time, the combustion products cannot be fully degassed, and voids occur. It was shown that the alternating three-step conditioning process including glass liquid forming in air, bubble removal under vacuum, and void filling-up in air can lead to void-free and uniform wafer bonding. The glass frit bonding samples with lots of voids/bubbles were compared to the ones without any defects.

Low Temperature Selective Epitaxy of Group-IV Semiconductors for Nanoelectronics

Continuous improvement of device performance is becoming very challenging as the transistor dimension approaches the physical limits of scalability. In particular, the source/drain (S/D) layer resistivity and contact resistance at the S/D region became major components for further parasitic resistance reduction [1]. Therefore, layers with high active doping concertation is required for future technology nodes. From another side, novel architectures such as 3D-stacked devices constraints the allowed thermal budget for epitaxy processes [2]. In this work, we will review our recent achievements on LT epitaxy for both Si:P and SiGe:B layers to enable (i) parasitic resistance reduction and (ii) novel integration schemes.All layers were grown in a 300 mm ASM reduced pressure chemical vapor deposition reactor on Si(001) substrates and patterned substrates.Firstly, we will discuss the benefits of SiP growth at low temperature leading to high active doping concentrations (~1.1×1021 cm-3), as reported in our previous work [3]. Figure 1 shows the omega-2theta scans around the symmetric (004) reflections of the Si:P/Si stacks. As expected, reducing the Si precursor flow leads to a higher substitutional P (~7.5%) incorporation in the layer. The good crystallinity of the SiP layer is attested by the well-defined thickness fringes. Figure 2a represents the XRR scans of non-selective SiP process and selective SiP process compared to 100 nm bare SiO2 on Si substrate. The presence of fringes (red curve) indicates that a 2D amorphous SiP layer is deposited on SiO2. To confirm the full selectivity of the process and the absence of nuclei on the SiO2 surface, top view SEM was performed (cf. Figure 2b).Afterwards, we will focus on the SiGe:B epitaxy at low temperature. Figure 3a shows omega-2theta scans around the symmetric (004) reflections of the SiGe:B/Si stacks for various B flows. The apparent Ge content drops from 52.1% to around 41.3% when B flow was multiplied by 16. The inset represents the reciprocal space map (RSM) around the asymmetric (224) peak of SiGe:B layers grown on Si(001) substrates with the highest B flow. The RSM clearly indicates high quality and fully strained SiGe:B layer. Figure 3b depicts the apparent Ge drop vs B flow. This reduction in Ge content is attributed to B strain compensation effect leading to artificially lower Ge content [4]. Figure 3c represents SiGe:B layer resistivity vs B flow. Resistivity drops until a critical B flow and then increases with increasing B flow. Figure 4 shows active doping concentration and Hall mobility as function of the B flow. The Hall measurements were performed on a cleaved wafer edge and assume a Hall scattering factor of 1. Active carrier concertation increases with increased B flow. As a side effect of the higher activation, the Hall mobility is lowered likely due to an increase in ionized impurity scattering which is the reason why the resistivity does not decrease substantially below a certain value for higher B flows at current growth conditions. Layers with similar physical properties have resulted in S/D metal contact resistivity of ~5×10-10 Ohm.cm2 [5]. Figure 5 depicts the selective process on advanced patterned nanosheet test structures. Figure 5a illustrates the selectivity towards several nanosheet structures, Figure 5b shows a zoomed in image indicating selective process towards inner SiN spacers and SiO2. Figure 5c is a FFT of the SiGe:B area indicated by red square and Figure 5d is an EDS map of the key elements (Si, Ge, O, C, Cl, F, N). Figure 6a and 6b show the selective process stability over 20 runs. The HR-XRD measurements at wafer center are represented in Figure 6a. Figure 6b represents the resistivity at the wafer center. Thickness uniformity across one of the wafer is illustrated in Figure 6c. The results indicate excellent wafer to wafer and within wafer uniformities despite low temperature processing.LT epitaxy offers several advantages to reach high active doping concentrations and enable novel integration schemes. Despite challenges associated to LT epitaxy, in this work we showed the possibility to grow selective layers while maintaining the excellent physical layer properties, within wafer uniformity and wafer to wafer reproducibility.[1] H. Wu et al. EEE International Electron Devices Meeting (IEDM), (2018), pp. 35.4.1.[2] A. Vandooren et al. IEEE Symposium on VLSI Technology, (2018), pp. 69-70.[3] R. Khazaka et al. ECS Meeting s, MA2020-02(24), (2020) 1734-1734.[4] J.M. Hartmann et al. ECS JSST, 3(11) (2014) 382.[5] H. Xu et al. IEEE Symposium on VLSI Technology, (2022), (to be published). Figure 1

Stress Relaxation in SGOI Structure Obtained by Condensation

The development of effective buffer layer has required years of work in order to obtain relaxed SiGe substrates [1]. However, main drawback of this approach relies on the presence of embedded and numerous dislocations which can be detrimental for optimal applications. Recently, a surprising relaxation phenomenon has been observed on specific Silicon-Germanium On Insulator (SGOI) structures [4-5].It has been observed that when the sample is heated, slippage is observed at the SGOI/Buried Oxide (BOX) interface.The phenomenon is not clearly understood. However, several explanations have been raised. It can be explained by the mechanical properties by Ge-O bonds which are weaker than the Si-O bonds at the SGOI/BOX interface causing the slip. [2] Also, the Ge atoms in the last crystalline layer at the BOX interface decreases the quantity of Si atoms inducing less bonds between the Si atoms of SGOI and the BOX.We suggest to take advantage of this phenomenon to obtain fully relaxed SGOI layers without dislocations. This new approach would allow to create high performance relaxed SGOI layers in industrial conditions with 300 mm wafers. This innovation is relevant for several applications, such as optical applications and the formation of base substrate to generate tensile Si epitaxy layer. It has to be noticed that any Ge concentration until pure GeOI structure is possible.Figure 1 shows the different process steps to obtain relaxed SGOI layer explained below. SiGe epitaxy (fig.1-a) is performed on an 300mm SOI wafer by Rapid Thermal Chemical Vapor Deposition (RT-CVD). Germane (GeH4) and Dichlorosilane (DCS) are used as precursor gases to obtain a 20nm thick fully strained Si0.8Ge0.2 layer. Upstream work is performed to improve the uniformity of the SiGe layer (thickness and composition) within the 300mm wafer. Indeed, they are key parameters impacting Ge concentration within wafer uniformity obtained after condensation.[3]Then, condensation is performed (fig.1-b) using thermal oxidation in a 300mm industrial furnace under N2/O2 atmosphere at 1000°C during several hours. Condensation is tuned to obtain the desired Ge concentration in the SGOI structure. Condensation allows to transform a SiGe/Si/BOX structure into SiGe/BOX structure called SGOI. Two mechanisms are involved in the condensation. The first mechanism is the Si-selective oxidation in the SiGe layer allowing Ge atoms to accumulate at the oxidation interface. The second mechanism is the Ge diffusion in the structure which allows SiGe inter-diffusion. The Ge atoms are maintained and homogenized in depth of the SGOI layer during the interdiffusion mechanism thanks to the BOX acting as a diffusion barrier. [2]During this work, the layer composition, the thickness as well as the stress were characterized by ellipsometry, XRR, XRD and SIMS. In addition, the surface was analyzed by AFM to detect any crystal defects.In this study, we propose to investigate the relaxation of SGOI layer with a concentration of Ge=50% because such structure shows no defects after condensation [2]. Thereafter, it will be possible to carry out GeOI in the future.Figure 2 shows SiGe thickness and density measurement by XRR. A thickness variation of 13.67 A and a density variation of 0.22g/cm3 of the SGOI layer after condensation on the whole wafer is obtained. The average density is 4,31g/cm3 with a concentration of %Ge=51% which was our target concentration.Then, the relaxation phenomenon is studied using anneals in the temperature range [700;900] °C during several hours. Indeed, we chose a temperature close to the SiO2 viscosity temperature and a long annealing time allowing to generate a slow slip thus limiting defects.Figure 3 shows a RSM map obtained by XRD of an Si0.5Ge0.5OI layer after annealing at 800°C for 2h. The mapping shows Si substrate as well as the layer relaxed along the (113) and (224) planes at an angle Φ=45°. RSM map allows to calculate the relaxation rate which is 22%. The relaxation on the sample is a success that remains to be improved by annealing time or temperatures to be optimized.This new approach would allow the realization a defect free relaxed SGOI layer under industrial conditions on a 300mm wafer. It would provide a new method for applications such as optical or the growth of tensile Si channels.[1] P.M.Mooney, Materials Science and Engineering, 1996[2] F.Roze. PhD thesis, 2018[3] D.Valenducq, PhD thesis, 2021[4] V.Boureau et al., ECS, 2018[5] Usuda, Koji, et al., Solid-State Electronics, 2013 Figure 1

Highest Quality and Repeatability for Single Wafer 150mm SiC CMP Designed for High Volume Manufacturing

Silicon Carbide (SiC) provides excellent characteristics such as superior thermal conductivity, high carrier mobility and extreme chemical stability in comparison with those of Silicon (Si). SiC is already showing significant device performance benefits in power devices, high performance communication, and LED lighting. However, SiC presents many challenges for wafer surface treatment because of its high hardness and remarkable chemical inertness. Today, mechanical polishing techniques on industrial batch CMP tools are the predominant methods for SiC wafer surface treatment, but material removal rate (MRR), surface defects and wafer flatness control are reaching fundamental limits with increasing wafer diameter. Batch processing typically results in a higher amount of surface scratches and defects, higher wafer to wafer variability, and higher wafer breakage rates. A unique single wafer chemical mechanical polishing (CMP) technique on 150mm n-doped, 4° off-axis, single crystal, 4H-SiC wafers was developed to create a virtually defect-free surface. A polishing head has been designed to manipulate polishing pressures at various zones of the wafer. This capability can modulate the removal thickness at each region on the wafer surface, resulting in a highly uniform wafer profile. Additionally, a CMP slurry has been formulated to maximize MRR from 2μm/hr to over 8.5μm/hr. Potassium permanganate has been selected as an oxidant and aluminum oxide particles as the abrasive. The oxidant concentration and abrasive content along with slurry pH level have also been optimized for ideal chemical and mechanical activity. Scratch-free wafer surfaces are observed with atomic force microscopy (AFM) and bright field (BF) and dark field (DF) inspection techniques. Roughness on the Si face is reduced to below 0.08nm. Total length of surface scratches was reduced to 10mm or less. Industrial metrics of wafer flatness, including total thickness variation (TTV) and local thickness variation (LTV) are modulated and improved. A test run completed on 25-wafers shows an overall 31% improvement of TTV post CMP process.

Surface Uniformity of Wafer-Scale 4H-SiC Epitaxial Layers Grown under Various Epitaxial Conditions

Wide band gap semiconductor 4H-SiC is currently widely used in the manufacture of high-frequency and high-voltage power devices. The size of commercial 4H-SiC wafers is increasing, from 4 inches to 6 inches. Surface roughness, as one of the parameters reflecting the quality of epitaxial wafers, is closely related to the performance of power devices. Most studies on the uniformity of epitaxial layers did not focus on RMS; however, the uniformity of epitaxial surface roughness also affects the device yield. In this paper, the root mean square roughness (RMS) and uniformity (σ) of epitaxial wafers are investigated as a function of epitaxy conditions, including C/Si ratio, growth temperature, and Si/H ratio. It was found that the best values of RMS and σ were obtained with C/Si ratio = 1 in the experimental range. Growth temperature had opposite effects on RMS and σ, with better RMS uniformity obtained at lower growth temperatures. An insignificant effect on RMS and σ has been found with the Si/H ratio changes in the experimental range. We hope that our experiments can play a certain role in promoting the improvement of the surface roughness of wafer-scale 4H-SiC epitaxial layers.

Fabrication of Large-Scale High-Mobility Flexible Transparent Zinc Oxide Single Crystal Wafers.

Single crystal wafers, such as silicon, are the fundamental carriers of advanced electronic devices. However, these wafers exhibit rigidity without mechanical flexibility, limiting their applications in flexible electronics. Here, we propose a new approach to fabricate 1.5 in. flexible functional zinc oxide (ZnO) single crystal wafers with high electron mobility (>100 cm2 V-1 s-1) and optical transparency (>80%) by a combination of thin-film deposition, a chemical solution method, and surficial treatment. The uniformity of the flexible single crystal wafers is examined by an advanced scanning X-ray diffraction technique and photoluminescence spectroscopy. The transport properties of ZnO flexible single crystal wafers retain their pristine states under various bending conditions, including cyclability and endurability. This approach demonstrates a breakthrough in the fabrication of the flexible single crystal wafers for future flexible optoelectronic applications.