Stress Relaxation in SGOI Structure Obtained by Condensation

Abstract

The development of effective buffer layer has required years of work in order to obtain relaxed SiGe substrates [1]. However, main drawback of this approach relies on the presence of embedded and numerous dislocations which can be detrimental for optimal applications. Recently, a surprising relaxation phenomenon has been observed on specific Silicon-Germanium On Insulator (SGOI) structures [4-5].It has been observed that when the sample is heated, slippage is observed at the SGOI/Buried Oxide (BOX) interface.The phenomenon is not clearly understood. However, several explanations have been raised. It can be explained by the mechanical properties by Ge-O bonds which are weaker than the Si-O bonds at the SGOI/BOX interface causing the slip. [2] Also, the Ge atoms in the last crystalline layer at the BOX interface decreases the quantity of Si atoms inducing less bonds between the Si atoms of SGOI and the BOX.We suggest to take advantage of this phenomenon to obtain fully relaxed SGOI layers without dislocations. This new approach would allow to create high performance relaxed SGOI layers in industrial conditions with 300 mm wafers. This innovation is relevant for several applications, such as optical applications and the formation of base substrate to generate tensile Si epitaxy layer. It has to be noticed that any Ge concentration until pure GeOI structure is possible.Figure 1 shows the different process steps to obtain relaxed SGOI layer explained below. SiGe epitaxy (fig.1-a) is performed on an 300mm SOI wafer by Rapid Thermal Chemical Vapor Deposition (RT-CVD). Germane (GeH4) and Dichlorosilane (DCS) are used as precursor gases to obtain a 20nm thick fully strained Si0.8Ge0.2 layer. Upstream work is performed to improve the uniformity of the SiGe layer (thickness and composition) within the 300mm wafer. Indeed, they are key parameters impacting Ge concentration within wafer uniformity obtained after condensation.[3]Then, condensation is performed (fig.1-b) using thermal oxidation in a 300mm industrial furnace under N2/O2 atmosphere at 1000°C during several hours. Condensation is tuned to obtain the desired Ge concentration in the SGOI structure. Condensation allows to transform a SiGe/Si/BOX structure into SiGe/BOX structure called SGOI. Two mechanisms are involved in the condensation. The first mechanism is the Si-selective oxidation in the SiGe layer allowing Ge atoms to accumulate at the oxidation interface. The second mechanism is the Ge diffusion in the structure which allows SiGe inter-diffusion. The Ge atoms are maintained and homogenized in depth of the SGOI layer during the interdiffusion mechanism thanks to the BOX acting as a diffusion barrier. [2]During this work, the layer composition, the thickness as well as the stress were characterized by ellipsometry, XRR, XRD and SIMS. In addition, the surface was analyzed by AFM to detect any crystal defects.In this study, we propose to investigate the relaxation of SGOI layer with a concentration of Ge=50% because such structure shows no defects after condensation [2]. Thereafter, it will be possible to carry out GeOI in the future.Figure 2 shows SiGe thickness and density measurement by XRR. A thickness variation of 13.67 A and a density variation of 0.22g/cm3 of the SGOI layer after condensation on the whole wafer is obtained. The average density is 4,31g/cm3 with a concentration of %Ge=51% which was our target concentration.Then, the relaxation phenomenon is studied using anneals in the temperature range [700;900] °C during several hours. Indeed, we chose a temperature close to the SiO2 viscosity temperature and a long annealing time allowing to generate a slow slip thus limiting defects.Figure 3 shows a RSM map obtained by XRD of an Si0.5Ge0.5OI layer after annealing at 800°C for 2h. The mapping shows Si substrate as well as the layer relaxed along the (113) and (224) planes at an angle Φ=45°. RSM map allows to calculate the relaxation rate which is 22%. The relaxation on the sample is a success that remains to be improved by annealing time or temperatures to be optimized.This new approach would allow the realization a defect free relaxed SGOI layer under industrial conditions on a 300mm wafer. It would provide a new method for applications such as optical or the growth of tensile Si channels.[1] P.M.Mooney, Materials Science and Engineering, 1996[2] F.Roze. PhD thesis, 2018[3] D.Valenducq, PhD thesis, 2021[4] V.Boureau et al., ECS, 2018[5] Usuda, Koji, et al., Solid-State Electronics, 2013 Figure 1