Wafer Stack Research Articles

Transmission bender for polarizing neutrons

A system of a polarizing solid state bender and a collimator was built and tested. The bender consists of a stack of thin silicon wafers coated with polarizing FeCo–Si supermirrors. The stack is deflected in the middle by one wafer thickness. Inserted in an unpolarized neutron beam this device works as a spin splitter by transmitting the spin down component without any change in its flight path and reflecting the spin up component. With a collimator behind the bender it can be selected which one of the spin components is transmitted. In this way a transmission polarizer for neutrons with wavelengths above 4 Å was built which has a total length of less than 10 cm.

Precision passive mechanical alignment of wafers

A passive mechanical wafer alignment technique, capable of micron and better alignment accuracy, was developed, fabricated and tested. This technique is based on the principle of elastic averaging: It uses mating pyramid (convex) and groove (concave) elements, which have been previously patterned on the wafers, to passively align wafers to each other as they are stacked. The concave and convex elements were micro machined on 4-in (100) silicon wafers using wet anisotropic (KOH) etching and deep reactive ion etching. Submicron repeatability and accuracy on the order of one micron were shown through testing. Repeatability and accuracy were also measured as a function of the number of engaged elements. Submicrometer repeatability was achieved with as little as eight mating elements. Potential applications of this technique are precision alignment for bonding of multiwafer MEMS devices and three-dimensional (3-D) interconnect integrated circuits (ICs), as well as one-step alignment for simultaneous bonding of multiple wafer stacks. Future work will focus on minimizing the size of the elements.

Thick-mode resonance of a PZT/Si wafer stack investigated by X-ray diffraction in Bragg geometry

X-ray diffraction in Bragg geometry was used to investigate the effects of standing longitudinal acoustic waves on an Si(111) wafer. A PZT/Si(111) stack with a resonant frequency of 2.34 MHz was constructed. In addition to the ultrasonic vibration, a thermal effect is evident. The thermal contribution causes an angular displacement of the Bragg profile and was mapped without time resolution. The actual ultrasonic oscillation of the surface was measured using a stroboscopic system. Bulging of the Si(111) surface was mapped out and the maximum deformation near the centre of the Si wafer was determined for a given ultrasonic power. Simple modelling using finite differences was helpful in determining the acoustic and thermal contributions.

EFFECTS OF WAFER BONDING AND THINNING PROCESSES ON ELECTRICAL PERFORMANCE OF MOS DEVICES

International Journal of Computational Engineering ScienceVol. 04, No. 02, pp. 323-326 (2003) Silicon MicromachiningNo AccessEFFECTS OF WAFER BONDING AND THINNING PROCESSES ON ELECTRICAL PERFORMANCE OF MOS DEVICESWENJIANG ZENG, HUAMAO LIN, XIAOLIN ZHANG, RAMASAMY CHOCKALINGAM, WEE CHONG HENG, SANGKI HONG and NARAYANAN BALASUBRAMANIANWENJIANG ZENGInstitute of Microelectronics, 11 Science park Road, Science Park II, Singapore 117685, Singapore Search for more papers by this author , HUAMAO LINInstitute of Microelectronics, 11 Science park Road, Science Park II, Singapore 117685, SingaporeTachyon Semiconductor (S) Pte Ltd, 11 Science park Road, Science Park II, Singapore 117685, Singapore Search for more papers by this author , XIAOLIN ZHANGInstitute of Microelectronics, 11 Science park Road, Science Park II, Singapore 117685, Singapore Search for more papers by this author , RAMASAMY CHOCKALINGAMInstitute of Microelectronics, 11 Science park Road, Science Park II, Singapore 117685, SingaporeTachyon Semiconductor (S) Pte Ltd, 11 Science park Road, Science Park II, Singapore 117685, Singapore Search for more papers by this author , WEE CHONG HENGInstitute of Microelectronics, 11 Science park Road, Science Park II, Singapore 117685, SingaporeTachyon Semiconductor (S) Pte Ltd, 11 Science park Road, Science Park II, Singapore 117685, Singapore Search for more papers by this author , SANGKI HONGInstitute of Microelectronics, 11 Science park Road, Science Park II, Singapore 117685, SingaporeTachyon Semiconductor (S) Pte Ltd, 11 Science park Road, Science Park II, Singapore 117685, Singapore Search for more papers by this author and NARAYANAN BALASUBRAMANIANInstitute of Microelectronics, 11 Science park Road, Science Park II, Singapore 117685, Singapore Search for more papers by this author https://doi.org/10.1142/S1465876303001186Cited by:0 PreviousNext AboutSectionsPDF/EPUB ToolsAdd to favoritesDownload CitationsTrack CitationsRecommend to Library ShareShare onFacebookTwitterLinked InRedditEmail AbstractThree-dimensional (3-D) wafer scale integration is a promising technique that can significantly alleviate interconnect delay problems, increase transistor-packing density and reduce manufacturing cost. It requires three key processes: wafer alignment, wafer bonding and wafer thinning. Among these three processes, wafer bonding process and wafer thinning process have been questioned whether these processes introduce in any degradation of device performance.In this paper, the effects of wafer bonding and wafer thinning processes on MOS device electrical performance are evaluated. Processes, which emulate those used for three-dimensional wafer scale integration, are employed for this study. Our preliminary results show that bonding process, which presses 200mm CMOS wafers by 10kN at 420°C for 40 minutes, has no obvious effect on MOS transistor electrical characteristics. We also demonstrated that device performance is not degraded after the wafer is thinned to 50 μm thick using back grinding and wet etch.Keywords:wafer scale integrationMOS devicesbondingthinningstacks References J. A. Davis, R. Venkatesan, A. Kaloyeros, M. Beylansky, S. J. Souri, K. Banerjee, K. C. Saraswat, A. Rahman, R. Reif and J. D. Meindl, "Interconnect Limits on Gigascale Integration (GSI) in the 21st Century", Proceedings of the IEEE, Vol. 89, No. 3 pp. 305 – 324 March 2001 . Google Scholar K. W. Lee, T. Nakamura, T. Ono, Y. Yamada, T. Mizukusa, H. Hashimoto, K. T. Park, H. Kurino, M. Koyanagi, "Three-Dimensional Shared Memory Fabricated Using Wafer Stacking Technology",The IEDM Tech. Dig., 2000, pp. 165-168 . Google Scholar M. Koyanagi, Y. Nakagawa, K. W. Lee, T. Nakamura, Y. Yamada, K. Inamura, K. T. Park and H. Kurino, "Neuromorphic Vision Chip Fabricated Using Three-dimensional Integration Technology", ISSCC Digest of Tech., pp. 272-273, Feb 2001 . Google Scholar H. Kurino, K. W. Lee, T. Nakamura, K. Sakuma, K. T. Park, N. Miyakawa, H. Shimazutsu, K. Y. Kim, K. Inamura and M. Koyanagi, "Intelligent Imaga Sensor Chip with Three Dimensional Structure", The IEDM Tech. Dig., 1999 pp. 879-882 . Google Scholar S. J. Abou-Samra, P. A. Asia, A. Guyot and B. Courtois, "3D CMOS SOI for High Performance Computing", Proceedings of the 1998 International Symposium on Low Power Electronics and Design, (ISLPED), pp. 54-58, August, 1998 . Google Scholar M. L. Campbell, S. T. Toborg and S. L. Taylor, "3-D Wafer Stack Neurocomputing", IEEE International Conference on Wafer Scale Integration, pp. 67-74, Jan., 1993 . Google Scholar M. Hendrix, S. Drews and T. Hurd, "Advantages of Wet Chemical Spin-Processing for Wafer Thinning and Packaging Applications", IEEE International Manufacturing Technology Symposium, pp. 229-236, 2000 . Google Scholar O. Siniaguine, "Atmospheric Downstream Plasma Etching of Si Wafers", IEEE International Electronics Manufacturing Technology Symposium, pp. 139-145, 1998 . Google Scholar Fan, A. Rahman and R. Reif, Electrochemical and Solid-State Letters 2(10), 534 (1999). Crossref, Google Scholar FiguresReferencesRelatedDetails Recommended Vol. 04, No. 02 Metrics History Keywordswafer scale integrationMOS devicesbondingthinningstacksPDF download

Neutron lens by superposition of glancing reflections

A neutron lens can lead to substantial intensity gains in neutron scattering experiments by imaging a source directly onto the sample. A design is proposed for a compact neutron lens made of a stack of silicon wafers, each coated with a neutron-reflective supermirror on one side and a neutron-absorbing layer on the other. We show that for imaging, the length of each mirror is a function of its distance from the optical axis, y, following a simple 1/y relationship. Uniform bending of the mirror assembly decreases the spatial aberration. The optimal design to minimize the optical spatial aberrations is discussed and Monte Carlo simulation results are presented.

Towards 0.1-mm spatial resolution in neutron diffractometry

A design goal for VULCAN, the SNS engineering neutron diffractometer, is to enable spatial mapping with 0.1-mm resolution. Because the targeted applications often involve the use of large samples or special environments, slits cannot be used for this purpose. In this paper, methods to achieve 0.1-mm spatial resolution are outlined. For the incident beam, a new compact focusing device is proposed. The device is made of a stack of bent silicon wafers, each having a reflective multilayer (supermirror) deposited on one side and a neutron-absorbing layer on the other side. The optimal design to minimize the optical spatial aberrations is discussed and Monte Carlo simulation results are presented. For the diffracted beam, imaging devices made from thick packets of diffracting bent silicon wafers (known as Bragg mirrors) could be used. The requirements to achieve sharp imaging together with a large phase-space acceptance window are discussed and preliminary testing results are presented.

A large-angle neutron polarisation analyser

A solid-state radial bender for the polarisation analysis of neutrons over a wide angular range was built and tested at BENSC. It consists of a bent stack of Si wafers, each coated with a polarising supermirror and an absorbing layer. The stack consisted of 19 channels tilted from each other by 0.19°; thus a total angular interval of 3.6° could be analysed. The device was mounted on a reflectometer detector arm with the bending axis parallel to the sample axis. With an incoming polarisation of 98.7%, a total flipping ratio of 70 and 60% transmission of the spin-up component were measured. Rotating the detector arm around the sample axis without a sample inserted shows that the expected angular range can be analysed. The transmission has an angular dependence due to the bender focusing properties. This effect does not occur parallel to the channels, where the geometry allows analysis over 9.5°. This was verified with a supermirror reflectivity curve. With such benders, neutron spins can be analysed for very large solid angles for small samples.

Passive and active microvibration control for very high pointing accuracy space systems

This paper presents the results of a two-year proof-of-concept program to prepare for the foreseen needs to master microvibrations on-board high pointing accuracy platforms, through the design, prototyping and experimental validation of four microvibration control systems: (1) an elastomer-based passive isolator for six degree-of-freedom isolation of a disturbance source (reaction wheel or mechanical cooler). Attenuation performance exceeding 20 dB above 25 Hz and 40 dB above 50 Hz has been demonstrated. (2) A passive vibration damping system, based on distributed piezoceramic wafers connected to a dissipative electrical circuit. Such simple, standalone devices are shown to have interesting applications (up 20 dB attenuation) when applied to the damping of a local flexible mode with concentrated strain energy. (3) Active damping with two-dimensional smart structures by using positive position feedback on pairs of collocated piezo-electric wafers used as sensors and actuators. Modal damping from 10 to 20 dB on the best controlled modes has been demonstrated, but some less controllable modes remain essentially undamped. (4) A centralized anti-phase control scheme operating on distributed sensors and actuators to compensate for stationary harmonic disturbances. The sensors are accelerometers and the actuators piezoelectric wafers or active struts equipped with a stack of piezoceramic wafers. The harmonic disturbance (for instance a reaction wheel unbalanced force) is estimated and compensated, with demonstrated attenuation from 30 to 40 dB. Follow-on activities in the domain are focused on the development of flight prototypes of the two active control concepts, for validation through on-orbit experimentation.

Challenges in plasma etching and patterning for fabrication of new systems and devices

Besides plasma etching of through-wafer interconnects in wafer stacks for vertical integration of chips [M. Engelhardt et al., Proceedings of the 23rd Annual Tegal Plasma Seminar (1997)] fabrication of Pt storage nodes with nontapered sidewalls is one of the most challenging tasks of plasma process technology today. In this work the fabrication of vertical Pt profiles was achieved by plasma processing with resist mask. In this novel approach, the buildup of thin redepositions of Pt onto the sidewalls of the resist, obtained as a result of processing in pure Ar plasmas, is utilized to achieve a sidewall steepness of the patterned Pt film which is determined by the steepness of the preetch resist profile. After pattern transfer and resist stripping, the portion of the redepositions protruding above the fabricated storage node was completely removed by chemical mechanical polishing.

Modern Applications of Plasma Etching and Patterning in Silicon Process Technology

Besides plasma etching of through-wafer interconnects in wafer stacks for vertical integration of chips, fabrication of platinum (Pt) electrodes with non-tapered sidewalls for the storage node in modern memories (DRAMs and FeRAMs) is one of the most challenging tasks of plasma process technology today. This paper describes the achievement of vertical integration of chips by plasma etching of high aspect ratio interchip vias. The etching processes for dielectrics, single crystal silicon, and the organic glue layer were all optimized for minimum reactive ion etching (RIE) lag i.e. for minimum decrease of etch rate with increasing etch depth. Furthermore the fabrication of perfect Pt electrodes for modern DRAMs and FeRAMs is reported. Vertical Pt profiles were achieved by plasma processing with resist mask. In this novel approach, the build-up of thin redepositions of Pt onto the sidewalls of the resist, obtained as a result of processing in pure Ar plasmas, is utilized to achieve a sidewall steepness of the patterned Pt film which is determined by the steepness of the pre-etch resist profile. After pattern transfer and resist stripping, the portion of the redepositions protruding above the fabricated storage node was completely removed by chemical mechanical polishing.

How boron incorporation during Si 1−x Ge x chemical vapor deposition degrades the Ge profile

The effect of boron incorporation during chemical vapor deposition of SiGe thin films from silane, germane, diborane, and hydrogen gas mixtures is investigated. It is shown that boron incorporation during SiGe thin-film growth degrades the Ge profile under certain growth conditions when the boron concentration is high enough (>1019 cm−3). In single-wafer atmospheric-pressure processes we find that no Ge concentration depression occurs at deposition temperatures above 675 °C. In multi-wafer atmospheric-pressure processes we find an increasingly occurring depression of the Ge concentration along the wafer stack, even at temperatures above 675 °C. In low-pressure processes, high-level in-situ doping of SiGe with boron is possible at temperatures as low as 550 °C without any degradation of the Ge profile. Thus LPCVD is superior to APCVD with respect to high-level in situ doping of SiGe with boron. The presence or absence of Ge profile degradation in boron-doped SiGe thin films is explained by the discussion of growth rate enhancement phenomena.

Transient heat transfer in batch thermal reactors for silicon wafer processing

Precise thermal control of multi-zone batch furnaces has become increasingly important in semiconductor industry to prevent defect generation during device fabrication. This work analyzes fundamental heat transfer processes during fast furnace ramping. Model simulations show two significant thermal features: (1) the radial temperature distribution on wafers follows a universal parabolic profile; and (2) a wafer stack produces a strong cavity effect for thermal radiation. An engineering model is developed based on these features to characterize the dependence of wafer temperature nonuniformity on processing conditions, including the ramp rate and wafer spacing. This simple yet accurate model is useful for real-time process control.

Three dimensional metallization for vertically integrated circuits: Invited lecture

The mainstream planar technology is marked by physical and technological limitations, which have a severe impact on system characteristics. The performance, the multi-functionality and the reliability of microelectronic systems will be mainly limited by the wiring between the ICs and subsystems. The “on-chip” wiring also leads to a critical performance bottleneck for future IC generations which can be solved only temporarily by the introduction of additional metallization layers and innovative materials (copper, low-ε-dielectrics). 3D IC fabrication creates a basis to overcome these drawbacks and to pave the way for system approaches of an entirely new quality. We realized a three dimensional metallization for V ertically I ntegrated C ircuits (VIC) using a newly developed technology that allows stacking and vertical interchip wiring of completely processed and electrically tested wafers using available microelectronic processes. Wafers are stacked by an aligned bonding process. Vertical electrical connections are formed between the uppermost metal levels of the bonded wafers by fabrication and metal refill of high aspect ratio interchip vias. This i nter c hip v ia (ICV) concept allows the formation of multiple wafer stacks using CMOS compatible materials and process steps exclusively and avoids wafer back processes. The potential of the ICV technology is the realization of some 100 000 vertical interconnects per cm 2 with 1–4 μm 2 interchip vias, arbitrarily selectable.

Wafer stacks as neutron monochromators

Abstract A recently developed process to create a spatially homogeneous but anisotropic mosaic structure in formerly perfect Ge wafers opened the way to combine these wafers to stacks and build large composite neutron monochromators for high resolution neutron powder and single crystal diffraction.

A Model for the Gas‐Phase Chemistry Occurring in a Furnace N 2 O Oxynitride Process

The nitridation of thin film oxides has been found to lead to enhanced device performance. Previous work by one of the authors has shown a falloff of nitrogen levels at the interface across the wafer stack in the direction of the gas flow, which was attributed to gas‐phase chemistry. The present work is a continuation of this investigation using a numerical solution of an enhanced reaction scheme. This work assumes that the primary gas‐phase species responsible for nitrogen incorporation into the oxide thin film is NO. The enhanced set shows that gas‐phase NO levels come into equilibrium over the time scales considered in a diffusion furnace using a purely chemical model. The presence of water is shown to affect the level of NO found at equilibrium, but does not show a monotonic falloff over time. The thermal kinetics are finally input into the chemistry model, taking into account gas temperature changes over time induced by endothermic and exothermic reactions. A simple model for heat transfer outside the system is used to investigate the rate of heating and cooling of the gas by the wall. The modified chemistry, together with the change in gas temperature due to this chemistry, is shown to be the likely source for the NO falloff observed previously.

A Monte Carlo Simulation Study of Radiation Heat Transfer in the Multiwafer LPCVD Reactor

A direct simulation Monte Carlo technique is used to simulate the radiation heat transfer in a multiwafer low pressure chemical vapor deposition (LPCVD) reactor. The model accounts for the heat transfer between the stack of closely spaced Si wafers, the quartz reactor tube, the stainless steel ends of the reactor, and the surrounding furnace. Spectral and thermal variations in the materials properties are included directly in the model. In addition, conductive heat transfer through the quartz tube is computed using a finite difference approach. The cooled ends of the reactor result in a suppression of the temperature of several wafers at each end of the wafer stack. Simulations show that the extent of this cooling effect is influenced by direct radiative heat losses from the end wafers as well as dissipation of the furnace heat flux by conductive heat losses through the quartz tube. The calculated temperature profiles are then used as thermal boundary conditions in simulations of rarefied gas flows in the LPCVD reactor. The thermal variations along the quartz and wafer surfaces give rise to significant temperature and density variations in the gas flow. The simulation results show excellent agreement with experimental data.

Using wafer stacks as neutron monochromators

A process to introduce a spatially homogeneous but anisotropic mosaic structure into thin, single-crystal wafers, which are then stacked and used as neutron monochromators, is described. The advantages compared to conventional techniques are good reproduceability, low cost and reduced risk of process failure. A focusing Ge(115) monochromator made from 24 wafer stacks was built for the high-resolution neutron powder diffractometer at the High Flux Beam Reactor at Brookhaven National Laboratory. Besides building “classical” monochromators for elastic neutron scattering experiments, individual wafers with a given peak reflectivity can be tilted with respect to each other to increase the reflected wavelength band Δλ/λ. Such “fanned” arrays present a competitive alternative to monochromators using highly-oriented pyrolitic graphite (HOPG).

3-D wafer scale architectures for neural network computing

We introduce a class of massively parallel computer architectures which can be configured to efficiently handle a variety of neural network models. The underlying technology is three-dimensional wafer scale integration (3-D WSI), which provides an ideal medium to construct powerful, compact, and low power hardware tailored for neural network processing. A second generation prototype computer consisting of a 128*128 array of processors formed by stacking 8 CMOS wafers is nearing completion. The performance of this prototype is compared with enhanced architectures configured with special wafer types to accelerate neural network operations. The design of these specialized resources emphasizes the synergy between neural processing functions and the 3-D WSI architecture and packaging. Detailed microcode emulations are used to assess the impact of different algorithm/architecture modifications. Neural networks for cooperative vision integration and multilayer backpropagation are mapped onto various 3-D wafer stacks. Estimated performance for the vision integration network is 2.4 billion connections per second. For the backprop network training algorithm, the performance ranges from 1.1 billion connection updates per second (GCUPS) for a near-term 128*128 prototype up to 53.4 GCUPS for a future 512*512 machine with more extensive neural processing hardware enhancements.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A Streamlined Technique for Preparation of Transverse Specimens for Transmission Electron Microscopy

ABSTRACTA procedure for batch processing of up to four specimens for cross-sectional transmission electron microscopy (X-TEM) has been developed. The technique is essentially an extension of the standard multi-slice composite full disc sample preparation method. However, disc cutting and dimple grinding steps have been eliminated. The trimming, gluing, stacking, and sectioning of the wafers from the original sample material to produce composite transverse sections are identical to those of the standard scheme. Grinding and polishing of the sections are carried out in a batch mode which, in turn, reduces the overall processing time per specimen. The prepared composite foils are mounted on metallic disc grids which provide structural support during ion thinning and microscopy.

Multilevel interconnections for wafer scale integration

Multilevel interconnections (MLIC) are the key to successful wafer scale integration (WSI). In this paper, we present a review of various approaches used in the implementation in MLIC to both monolithic WSI and wafer scale hybrid packaging. Electrical interconnections using both thin (micron dimensions) and thick (tens of microns dimensions) dielectric and metal films are discussed from a performance standpoint. The advantages of the thick film approach for realizing transmission line performance is indicated. Techniques for implementing thick electrical interconnections such as plate‐up, via etching and lift‐off, are described. This treatment includes silicon‐die‐on‐wafer, silicon‐die‐on‐ceramic, and GaAs‐on‐silicon wafer hybrids. Fabrication approaches which have been explored by several research groups are compared. Some projections concerning yield of the wafer interconnections are calculated. Finally, a brief examination of some potential approaches to three‐dimensional stacking of wafers is made, including two‐sided population of wafers.