Wafer Scanning Research Articles

The Photoelastic Constant of (0001) 4H Silicon Carbide Determined by Scanning Infrared Polariscopy

The piezo‐optic coefficients (π11‐π12) and the photoelastic constant Cσ of on‐axis (0001) 4H silicon carbide at λ = 1.3 μm are determined to (−3.3 ± 0.5) × 10−13 and (−2.8 ± 0.4) × 10−12 Pa−1, respectively. The experiment is conducted using a scanning infrared depolarization imager (SIRD) that uses a rotational mode for wafer scanning equipped with a special calibration setup for diametrical loading of 150 mm diameter wafers. The loading force is varied by gradually setting the wafer rotation frequency. (π11–π12) and Cσ are determined by analyzing the dependence of the shear stress equivalent on the loading force in the wafer center. This calibration procedure is made difficult by the pronounced inhomogeneous defect distribution on the wafer under study. Furthermore, the unloaded wafer is characterized using the multipolarization analysis on the base of an eccentric measurement mode. The resulting map of the shear stress maximum τmax completed by the direction of the large principal stress component reveals that the outer wafer part is tensile stressed in circumferential direction like a ring with magnitudes up to 10 MPa.

Combined Feedforward Control and Disturbance Rejection Control Design for a Wafer Stage: A Data-Driven Approach Based on Iterative Parameter Tuning

This article presents a data-driven algorithm that combines the advantages of iterative feedforward tuning and disturbance rejection control to satisfy the precision requirements and ensure extrapolation capability of wafer scanning. The proposed algorithm differs from pre-existing algorithms in terms of its low requirement of system model, high extrapolation capability for non repetitive trajectory tracking tasks, and high tracking precision. The feedforward controller is tuned based on instrumental variables. It utilizes tracking errors from past iterations to eliminate reference-induced errors without requiring a system model. Meanwhile, the system inverse is approximated during iterative process, and then a disturbance rejection control based on iterative tuning is constructed to compensate for disturbance-induced errors. The proposed algorithm is applied to a wafer stage. The experimental results validate the effectiveness and superiority of the proposed algorithm.

(Invited) Influence of Wafering, CMP and Subsurface Damage on Epitaxial Defects and Surface Quality in SiC

The Silicon Carbide power device industry continues to experience very robust increases and adoption in many long-term growth markets like renewables, cloud and electric vehicles. The continuous year over year increases in demand has led to widespread raw material shortages of substrates and epi wafers. This has resulted in incumbent manufacturers putting in more capacity and the emergence of many new SiC substrate manufacturers. With many supply sources, there is also a wide variety of quality in the material. In some of our previous works, we have looked at some of the issues arising from immature crystal quality. However, often overlooked as a source of defects and surface quality, is the damage left over from wafering, grinding and CMP. In this work, we observe the effects of sub-surface damage and how it affects epitaxial layer quality. We also look at ways to minimize this effect both at the CMP stage and at the epi growth stage. Defect metrology tools for Silicon Carbide wafers have seen great improvements in capability and throughput. As wafers are measured both pre-epi and post-epi, a wide category of defects are identified and classified. Full wafer scans for substrates yield several defect categories like micropipes, bumps/particles as well as shallow and deep scratches. Recent tools with photoluminescence (PL) are also able to detect crystal defects like grain boundaries and bar stacking faults among others. All of these defects have an effect on the epitaxial layers either nucleating or transforming into other defects. However, none of the detection methods are able to detect residual damage left over from the wafering/grind process. This damage can be present just below the surface even if the surface is extremely smooth and scratch free. We detect the presence of these damage layers after epitaxial growth. Depending on the amount of damage present a very high density of stacking faults and triangular defects (and partials) are seen in the epitaxial layers. To remove the damage layers, a higher amount of CMP removal was used. As the damaged layer is reduced, the nucleation of the stacking faults and triangular defects also reduce. In some wafers, we observe some residual damage layers present near the wafer edges and flats where the CMP process is not uniform. Moreover, even when the nucleation of the defects are suppressed, the resulting epi is much rougher than epi grown on a substrate without any sub-surface damage. Wafers that displayed sub-surface damage were re-polished back to the substrate using a known good process. These wafers did not show the nucleation of defects. The suppression of the nucleation of defects was also attempted by enhanced in-situ etching before epi growth. Though this resulted in suppression of nucleated defects, by removal of the damage layer, it also resulted in much rougher epitaxial layers. The characterization results and processes from these experiments will be presented. Additional methods to detect these damage layers will be discussed.

Data-Driven Iterative Feedforward Tuning for a Wafer Stage: A High-Order Approach Based on Instrumental Variables

The feedforward controller plays an important role in the achievement of high servo performance of wafer scanning. In this paper, a novel data-driven feedforward tuning method is developed in the presence of noise. Three distinguished features make it different from the existing methods: first, high extrapolation capability to tasks; second, low requirement on the system model; and especially, third, high noise tolerant capability. These superiorities are achieved by a high-order iterative feedforward tuning algorithm based on instrumental variables. It utilizes error data from all past iterations via an integrator in the learning law, yet without the need of the plant model or the sensitivity function. Furthermore, $H_2$ optimization with specified convergence speed constraint is proposed to design the learning gain. Connections and differences between the proposed algorithm and the existing ones are discussed. Experimental results validate the proposed method and confirm its effectiveness and superiority.

Design of arbitrary-order robust iterative learning control based on robust control theory

Iterative learning control (ILC) is an effective technique that improves the tracking performance of systems by adjusting the feedforward control signal based on the memory data. The key in ILC is to design learning filters with guaranteed convergence and robustness, which usually involves lots of tuning effort especially in high-order ILC. To facilitate this procedure, this paper proposes a systematics approach to design learning filters for arbitrary-order ILC with guaranteed convergence, robustness and ease of tuning. The filter design problem is transformed into an H∞ optimal control problem for a constructed feedback system. This approach is based on an infinite impulse response (IIR) system and conducted directly in iteration-frequency domain. The proposed algorithm is further advanced to the one that explicitly considers system variations based on μ synthesis. Important characteristics of the proposed approach such as convergence and robustness are explored and demonstrated through both simulations and experiments on a wafer scanning system.

Measurement of volt-ampere characteristics of the SiPM on wafer level with setup based on the PA200 BlueRay probe station

Setup for measurement of volt-ampere characteristics of the Silicon photomultipliers (SiPMs) on wafer level consisting of the probe station PA200 BlueRay with embedded computer and SourceMeter Keithley 2400 was built. The setup is controlled by the homegrown software which allows adjustment of the measurements accuracy and speed. Firstly, complete I-V curves for a few samples of the chosen SiPM structure on the wafer are measured. Based on it the range of breakdown voltage and current level are defined which are used to correct the software settings. After that the whole wafer scan is made. The resulting I-V curves are used for SiPM selection (sorting) by current value at some predefined overvoltage (the difference between applied voltage and the breakdown one). Breakdown voltage is defined as: max ((dI/dU)/I).

Full-Wafer Voltage Contrast Inspection for Detection of BEOL Defects

This paper details an application where E-beam inspection (EBI) can be used for 100% full wafer inspection, generally considered a mythical target for EBI. For process layers where the line-widths and defects of interest are large, very large pixel size and high scan frequency can be used, thereby making full wafer inspection feasible. The metal layers in the back-end-of-line fit this bill when scanned in voltage contrast (VC) mode. Shorts or opens at any previous layer connected to the surface nodes can cause a VC signal, therefore the electrical health of each wafer is assessed for multiple layers simultaneously across the full wafer. The advantage of this scan is that failure sites can be identified and somewhat localized well before wafer final test. This application is more appropriate for semi-mature technologies where there are few defects per wafer, and therefore a full wafer scan is needed to catch a reasonable number of defects. The challenge with this type inspection is in identification of the root cause. A number of studies to map VC defect strength to types of physical defects are described. These studies demonstrated that this technique successfully finds yield limiting defects, but not all yield limiting defects will be detected. A plan for how to use the VC inspection to find root cause is presented.

(Invited) Enabling SiC Yield and Reliability through Epitaxy and Characterization

Silicon Carbide offers a compelling alternative for power devices. Its multiple uses in power efficient applications have led to a rush in commercialization of various device families. The major issues facing widespread adoption of SiC devices are cost and reliability. There are many facets to achieving and meeting consumer expectations in both these areas. One important part of reducing cost is moving to larger diameter substrates. This is currently challenging due to the lack of sufficient quality in 150mm wafers compared to 100mm wafers. Though quite some progress has been made on 150mm substrates, they still have a much larger number of crystal defects and macro defects than mature 100mm substrates. This leads to more concerns regarding reliability issues related to crystal defects in the substrates and subsequently in the epitaxial layers. This work focuses on ways of mitigating reliability issues while still leveraging the use of 150mm material. One facet of the reliability is dealing with defects that can cause bipolar degradation after stress [1,2]. These affect not just bipolar switches like BJTs but also the body diode of the MOSFETs. There are many approaches like buffer layers, pre-treatments, growth interrupts etc. to reduce these defects in the epi and prevent their propagation into the active layers. However some defects do make it through to the active layers. Traditional methods of detecting these defects like Basal Plane Dislocations (BPDs) are destructive in nature like molten KOH etching. Even this method is lacking since it only exposes the defects that break the surface of the epitaxial layers. Many of these BPDs can get converted to threading edge dislocations in the active regions and are therefore never detected by KOH etching. Recently many groups have started using Infra-Red Photoluminescence (IR PL) (700nm+) to detect both the basal plane dislocations and stacking faults [3-5] utilizing full wafer scans. In one of our previous works [6], we have used a similar method to screen out die that would exhibit degradation under forward bias stress. There are however some cases where the detection and screening using this method becomes challenging. This happens when the defects propagate in the buffer layer to just below or just into the active layer. This is because there is a lack of PL signal from the typically high doped buffer layers. This results in no signal or extremely faint PL signals coming from the buffer layers. As other research groups [7] have shown these defects in the buffer near the interface, have the tendency to expand into the active regions as a result of carrier recombination, thus killing or degrading the device performance. The solution to this problem is using the Near Ultra Violet PL spectrum to detect the crystal defects in the SiC material. The defects are detected as an absence of bandgap recombination spectra and thus detect any defects that cause non-radiative recombination. The BPDs are clearly detected even in highly doped buffer regions with sufficient SNR along with brighter features of the BPDs in the active layers. This stronger signal along with the longer overall length enables automated detection, classification and screening of the required defect types and provides visibility into the conversion efficiency of the buffer layers. This gives a very fast feedback path for epitaxial development to reduce the presence of these defects in the active regions. Traditionally a thorough feedback loop would involve fabricating and stressing PN diodes on the epi, which takes multiple weeks [6]. Other types of crystal defects like grain boundaries that are more prevalent in less mature 150mm substrates can also be detected using this method. This enables the identification of defective regions and defective wafer batches, thereby providing a fast and non-destructive feedback loop to the substrate vendors. A combination of these methods enables the confident use of 150mm substrates while maintaining the reliability expectations of the device customers. Results from improved quality epitaxial layers on both 100mm and 150mm substrates will be presented. Comparison and validation of the defect scan data to molten KOH etching will also be presented. [1] A. Agarwal et al. Mater. Sci. Forum, 527-529, pp1409-1412 (2006) [2] L. Farese et al. Mater. Sci. Forum, 645-648, pp1037-1040 (2010) [3] T. Tanaka et al. Mater. Sci. Forum, 778-780, pp91-94 (2014) [4] M. Odawara et al. Mater. Sci. Forum, 778-780, pp382-385 (2014) [5] S. Yamamoto et al. Mater. Sci. Forum, 778-780, pp951-954 (2014) [6] B. Buono et al. Mater. Sci. Forum, 778-780, pp1017-1020 (2014) [7] N. A. Mahadik et al. Appl. Phys. Lett. 100, 042102 (2012)

Magnet assisted stage for vibration and heat reduction in wafer scanning

Wafer scanning stages must deliver high accelerations/decelerations at motion reversals to achieve high productivity. The resulting inertial forces cause vibration of the machine frame and overheating of the linear motor actuators, thus diminishing the accuracy and increasing the cost of the stages. The novel stage design presented in this paper uses magnetic repulsion to provide assistive forces to the linear motors during acceleration/deceleration to reduce actuation force requirements and overheating. Vibration is reduced by transmitting the assistive forces to the ground, not the machine frame. 66% and 55% reduction in vibration and heat, respectively, are demonstrated using a prototype stage.

Modelling slip flow in micro/nano gaps with moving boundary

The analytical solution models have been constructed to describe the slip flow in the micro/nano gaps with moving boundary, including the case of immersion lithography. The two-dimensional computational fluid dynamics models are established to validate them. The results show that the slip flow varies with time and tends to a steady state quickly. The transient and steady states are investigated respectively to overall describe the slip flow, and there are significant differences between the slip and non-slip flow. Moreover, the stationary liquid on moving wall may be generated when the direction of pressure-driven flow is opposite to the direction of shear flow. This phenomenon is important to prevent liquid leakage during wafer scanning, and the corresponding parameters are optimized to improve the quality of advanced immersion lithography.

Stability of Current Gain in SiC BJTs

In this work, large area SiC BJTs with good long-term stability in 1000 hrs DC stress tests are demonstrated. It is also illustrated how wafer scanning techniques can be used to reject BJT dies with basal plane dislocations, thereby eliminating the risk for bipolar degradation.

Behaviors of Immersion Flow in Micro-Gap with Moving Boundary

In order to improve the flow stability when wafer scans at high speed, immersion lithography with small flow-thickness is proposed for the high resolution lithography. By using the three-dimensionally numerical methods, the immersion flow in micro-gap is investigated to analyze the behaviors of liquid flow. Based on the flow characteristics of typical structures with different liquid thickness and scanning speed, the liquid mean-velocity on account of thousand sample points in the exposure area are studied, and the appropriate parameters and method of effective renovation with small thickness are also given.

Flow Characteristics for High-Speed Scanning in Immersion Lithography

High-speed scanning is an effective way to improve the throughput of immersion lithography with double patterning, especially when the critical dimension is less than 32-nm. But it makes more complex characteristics of immersion flow. In this paper, considering the extreme speed of wafer scanning, the model is developed to investigate the characteristics of immersion flow, including the velocity vector, pressure distribution, renovation efficiency and so on. Finally, the optimized parameters and methods to effective liquid renovation are proposed when the wafer scans at high-speed.

Effect of Injection Parameters on Immersion Liquid during Wafer Scanning

Double patterning improves the development of immersion lithography, but it brings new challenges including the higher scanning velocity of wafer. In this paper, considering two typical injection types, the three-dimensional computational fluid dynamics model is developed to investigate the effect of injection parameters on immersion liquid during wafer scanning. By analyzing the velocity distribution of immersion flow and normal stress on the lens, the proper parameters of injection are proposed under the typical conditions, and the appropriate parameters which lead to effective renovation with low lens distortion are also given.

Lens distortion for liquid renovation in immersion lithography

Liquid renovation is perhaps the best method to reduce contamination in immersion lithography, but it brings lens distortion because of the high density and viscosity of the immersion liquids compared to air. In this paper, considering wafer scanning, the three-dimensional computational liquid dynamics model and finite-element model are developed to investigate the lens distortion for immersion liquid renovation. After analyzing the influence of wafer scanning directions, the empirical formulas of the lens distortion for three-dimensional model are established to describe the effect of the parameters of lens and polymer which are used to mount lens and the parameters of immersion liquid flow on lens distortion.

Investigation on the critical velocity for liquid loss in immersion lithography

Immersion lithography seeks to extend the resolution of optical lithography by filling the gap between the final optical element and the wafer with a liquid characterized by a high index of refraction. The semiconductor industry demands high throughput, leading to relatively large wafer scanning velocities and accelerations. For higher scanning velocities, an issue that has been identified is the deposition of the immersion liquid while confining a relatively small amount of liquid to the under-lens region. Liquid loss occurs at the receding contact line that forms when a substrate is withdrawn from a liquid, which potentially leads to defects on printed patterns. There has been substantial prior work relative to understanding and building semi-empirical correlations and numerical models to investigate this behavior of the receding three-phase contact line. In the current work, a new liquid injection and collection model with analytic solutions is presented and compared with experimental results, in which the critical velocity for liquid loss is mainly a function of the vacuum degree, the injection flow rate, the properties of the immersion liquid. This correlation allows the critical velocity to be predicted with a given gap height between wafer and lens using only a measurement of the injection speed and knowledge of the fluid properties. Experimentally, glycerin–water mixtures of varying viscosities and different injection flow rates were tested, with variable outlet vacuum degree and inlet speed, showing a mean average error within 12%. This correlation represents a useful tool that can serve to approximately guide the development of fluid control for immersion systems as well as to evaluate alternative immersion fluid candidates to minimize liquid deposition while maximizing throughput.

Modeling fluid velocity response for wafer scanning in immersion lithography

In order to improve optical lithography resolution, a method has been proposed to insert a high refraction index liquid in the space between the lens and the wafer in place of the low refractive index air that currently fills the gap. During exposure period, the scanning process of wafer is repeated many times on a typical wafer, and the immersion liquid motion is greatly influenced by it. As a nominally scanning time of wafer is short (<0.1 s), the unsteady effect cannot be ignored, which play an important role in the immersion liquid renovation and optical birefringence. Considering the unsteady effect induced by the scanning process of wafer, models have been established to describe the limited flow field between the lens and the wafer.

Photoresist removal using an O2∕N2 medium pressure plasma jet with high speed wafer scanning: Unimplanted resist studies

The authors describe a plasma ashing system where a stationary jet of hot, activated gases removes photoresist from a scanning wafer. The jet is created by a reactant stream flowing through a 2.45GHz surface wave discharge in a 6mm quartz tube. For O2∕N2 plasmas in the medium pressure range from 20to100Torr, a luminous plasma jet emerges from the end of the discharge tube that transports both heat and reactive species to the wafer. A single scan results in a Gaussian track profile with a standard deviation of 7mm for the source-to-substrate distance of 9mm. A simple model of the ashing process, which assumes a thermally activated ash rate and Gaussian distributions for both power density and reactant flux, unifies the dependence of effective ash rate on the substrate temperature and scan speed at a constant power. The best fit activation energy at 2.5kW is 0.23eV, about half of the value found in conventional downstream ashing, implying that diffusion plays a significant role in limiting the ash rate. The peak thermal power density in a 2.5kW jet at 80Torr is 160W∕cm2, resulting in an effective instantaneous ash rate of 2.5mm∕min for a scan speed of 70cm∕s and 200°C chuck temperature. This implies that the time to clear a 1.2μm thick resist coating from a 300mm wafer is 18s.

Characteristics of High Power Laser Shock Waves and Their Cleaning Performance

Plasma shock waves induced by focusing a Q-switched Nd:YAG laser at a maximum energy of 1.8 J in air were characterized by a laser beam deflection method and applied to the particle removal. The dimension of plasma plume and velocities of shock waves were measured as a function of laser energy and gap distance. The shock wave velocity decayed rapidly as the gap distance increased. The laser shock wave cleaned area followed the shape of shock waves, which was heart-shaped. The shorter gap distance, the higher particle removal efficiency (PRE) was observed. PRE of 98% was achieved by optimizing the laser energy, gap distance, and wafer scanning procedure.

Evaluation of an In-Situ Particle Monitoring System on an MxP Plasma Etch Tool

Etching is the process where a layer is removed from a wafer surface through openings in a photoresist pattern. To monitor this process, a surface scan was employed. An in-situ particle monitor (ISPM) was installed on a plasma etch tool. The ISPM was incorporated so engineers and technicians could gain real-time information and notification of what is happening inside this tool during processing. Since ISPMs are real-time, they can catch problems as they are occurring. The ISPM detected two major problems on the plasma etch tool within a 3-wk period. The wafer scan data were monitored during this same time frame.