Wafer Manufacturing Research Articles

Multilayer Graphene-Coated Silicon Carbide Nanowire Formation Under Defocused Laser Irradiation

Graphene-coated silicon carbide (SiC@C) core–shell nanostructures have attracted attention in the fields of energy storage and nanoelectronics. In this study, multilayer graphene-coated silicon carbide (SiC) nanowires were obtained through the laser irradiation of a mixture target of graphite powder and silicon (Si) grinding sludge discharged from Si wafer manufacturing. Laser irradiation was performed using an ytterbium (Yb) fiber pulsed laser with a pulse width of 10 ms and a wavelength of 1070 nm with various defocus distances. The effect of laser defocusing on the morphology of the generated nanostructures was investigated. Results showed that nanowires were produced under the defocused conditions, and nanoparticles were observed at the on-focus position. The products obtained under all defocused conditions showed a core–shell structure, and the SiC nanowires were covered by graphene layers. The aspect ratio of the nanowires increased with the defocus distance. Observation of the laser-induced plume using a high-speed camera showed that when the laser was defocused, the plume propagation speed slowed down, and the shape of the plume changed to a swirling vortex. The nanowire formation was closely related to the propagation speed and shape variation of the plume. This successful production of SiC@C core–shell nanowires from Si waste opens up the possibility of the sustainable development of new materials for energy storage and nanoelectronics.

Development of Fault Detection Systems: The Hadoop Ecosystem Implementation

Semiconductor manufacturing relies on a long and complex production line for wafer fabrication. In a modern semiconductor fabrication plant (fab), a wafer manufacturing line is composed of more than 1,000 manufacturing tools and an overhead hoist system for delivering wafer lots among the tools. Novel technologies, such as Internet of Things (IoT) and software engineering technologies, are adopted in semiconductor manufacturing such that large amounts of data can be collected from manufacturing tools. Also, these tools and the overhead hoist system should cooperate well with each other. Due to the data-processing capacity limitation in a current fault detection and classification (FDC) system, the diagnosis efficiency is limited such that some undesired events cannot be detected in time, leading to significant economic loss. With the booming development of big data technology, this work conducts a study on a new FDC framework based on a Hadoop ecosystem to deal with the data-processing limitation and improve diagnosis efficiency. Also, a migration path is presented such that the current FDC system can be smoothly migrated to a Hadoop ecosystem-based one without shutting down a wafer fabrication line. Experimental results show that the proposed FDC framework can run safely and stably.

A Distributed Supervisor Architecture for a General Wafer Production System.

The current trend in the wafer production industry is to expand the production chain with more production stations, more buffers, and robots. The goal of the present paper is to develop a distributed control architecture to face this challenge by controlling wafer industrial units in a general production chain, with a parametric number of production stations, one robot per two stations where each robot serves its two adjacent production stations, and one additional robot serving a parametric number of stations. The control architecture is analyzed for individual control units, one per robot, monitoring appropriate event signals from the control units of the adjacent robots. Each control unit is further analyzed to individual supervisors. In the present paper, a modular parametric discrete event model with respect to the number of production stations, the number of buffers, and the number of robotic manipulators is developed. A set of specifications for the total system is proposed in the form of rules. The specifications are translated and decomposed to a set of local regular languages for each robotic manipulator. The distributed supervisory control architecture is developed based on the local regular languages, where a set of local supervisors are designed for each robotic manipulator. The desired performance of the total manufacturing system, the realizability, and the nonblocking property of the proposed architecture is guaranteed. Finally, implementation issues are tackled, and the complexity of the distributed architecture is determined in a parametric formula. Overall, the contribution of the present paper is the development of a parametric model of the wafer manufacturing systems and the development of a parametric distributed supervisory control architecture. The present results provide a ready-to-hand solution for the continuously expanding wafer production industry.

Measurement of the Kerr Nonlinear Refractive Index and its Variation Among 4H - SiC Wafers

The unique material property of silicon carbide ($\mathrm{Si}\mathrm{C}$) and the recent demonstration of low-loss $\mathrm{Si}\mathrm{C}$-on-insulator integrated photonics platform have attracted considerable research interests for chip-scale photonic and quantum applications. Despite the impressive progresses made in $\mathrm{Si}\mathrm{C}$ photonics, some of its beneficial photonic properties are yet to be fully explored. Here, we carry out a thorough investigation of the Kerr nonlinearity among $4H$-$\mathrm{Si}\mathrm{C}$ wafers from several major wafer manufacturers, and reveal that their Kerr nonlinear refractive index can be significantly different. By eliminating various measurement uncertainties in the four-wave mixing experiment, the best Kerr nonlinear refractive index of $4H$-$\mathrm{Si}\mathrm{C}$ wafers is estimated to be approximately 4 times, instead of the prior estimate of 2 to 3 times, of that of stoichiometric silicon nitride in the telecommunication band. In addition, experimental evidence is developed that the Kerr nonlinearity in $4H$-$\mathrm{Si}\mathrm{C}$ wafers can be stronger along the $c$ axis than that in the orthogonal direction. Our examination of the Kerr nonlinear refractive index also compels a useful correction to the existing model in high-index-contrast waveguides; otherwise, considerable errors can be introduced.

A full-flow inspection method based on machine vision to detect wafer surface defects.

The semiconductor manufacturing industry relies heavily on wafer surface defect detection for yield enhancement. Machine learning and digital image processing technologies have been used in the development of various detection algorithms. However, most wafer surface inspection algorithms are not be applied in industrial environments due to the difficulty in obtaining training samples, high computational requirements, and poor generalization. In order to overcome these difficulties, this paper introduces a full-flow inspection method based on machine vision to detect wafer surface defects. Starting with the die image segmentation stage, where a die segmentation algorithm based on candidate frame fitting and coordinate interpolation is proposed for die sample missing matching segmentation. The method can segment all the dies in the wafer, avoiding the problem of missing dies splitting. After that, in the defect detection stage, we propose a die defect anomaly detection method based on defect feature clustering by region, which can reduce the impact of noise in other regions when extracting defect features in a single region. The experiments show that the proposed inspection method can precisely position and segment die images, and find defective dies with an accuracy of more than 97%. The defect detection method proposed in this paper can be applied to inspect wafer manufacturing.

Data-Driven Modelling and Robust Control of a Semiconductor Manufacturing Process

The paper presents a model-based controller design technique for a thermal process in silicon wafer manufacturing. The underlying model is obtained by dynamic mode decomposition which is a purely data-driven approach. The control scheme consists of a state feedback controller in combination with a disturbance observer, which allows robust tracking of feasible reference temperature profiles. The approach is validated using a laboratory setup.

Forecasting the yield of wafer by using improved genetic algorithm, high dimensional alternating feature selection and SVM with uneven distribution and high-dimensional data

AbstractWafer yield prediction, as the basis of quality control, is dedicated to predicting quality indices of the wafer manufacturing process. In recent years, data-driven machine learning methods have received a lot of attention due to their accuracy, robustness, and convenience for the prediction of quality indices. However, the existing studies mainly focus on the model level to improve the accuracy of yield prediction does not consider the impact of data characteristics on yield prediction. To tackle the above issues, a novel wafer yield prediction method is proposed, in which the improved genetic algorithm (IGA) is an under-sampling method, which is used to solve the problem of data overlap between finished products and defective products caused by the similarity of manufacturing processes between finished products and defective products in the wafer manufacturing process, and the problem of data imbalance caused by too few defective samples, that is, the problem of uneven distribution of data. In addition, the high-dimensional alternating feature selection method (HAFS) is used to select key influencing processes, that is, key parameters to avoid overfitting in the prediction model caused by many input parameters. Finally, SVM is used to predict the yield. Furthermore, experiments are conducted on a public wafer yield prediction dataset collected from an actual wafer manufacturing system. IGA-HAFS-SVM achieves state-of-art results on this dataset, which confirms the effectiveness of IGA-HAFS-SVM. Additionally, on this dataset, the proposed method improves the AUC score, G-Mean and F1-score by 21.6%, 34.6% and 0.6% respectively compared with the conventional method. Moreover, the experimental results prove the influence of data characteristics on wafer yield prediction.

Control of dislocation clusters by artificially-introduced micro-twins in cast-mono silicon

Cast-mono silicon (CM-Si) is a promising method to fabricate cost-effective photovoltaic silicon wafers, and dislocation clusters are currently one of the most detrimental defects in CM-Si. Once formed, they propagate rapidly and unlimitedly in the single crystalline lattice and then serve as strong recombination centers and shunts in solar cells, which severely influence the crystal quality and cell performance. This work innovatively introduces a method to restrain and modulate the propagation of dislocation clusters during CM-Si growth. The constitutional supercooling effect was induced in CM-Si by performing boron-indium co-doping to generate harmless micro-twins. Related characterizations are mainly focused on the microstructure as well as electrical properties of wafers. In addition, an interaction model that suggests micro-twins’ formation and the interaction with dislocations was proposed. The results show that these micro-twins grow in preferred 〈112〉 orientations so they can partially block the growth and propagation of dislocation clusters within the 〈110〉 directions, and the recombination-active defects at the upper crystal were remarkably redistributed. The density and area of the detrimental defects were decreased. We think these conclusions could offer strategies for silicon wafer manufacturers, and we hope the physical mechanism might intrigue the insights for other crystalline growth.

Formulation of research and development strategy by analysing patent portfolios of key players the semiconductor industry according to patent strength and technical function

Silicon wafer is the base material of chips and is an important manufacturing technology in semiconductor industry. This research conducts international patent analysis of five major patentees, SUMCO, Shin-Etsu, GlobalWafers, Siltronic, and SK Siltron, also the top five global silicon wafer manufacturers in the world, in order to get research and development strategy.Qualitative and quantitative analysis of technology and means on entire industry as well as individual companies are visualized by technology means matrix, comprehensiveness, and relative patent advantage index. Two categories of indicators of “Patent Portfolio Strength” and “Patented Technology Strength” are calculated, and the patent portfolios of assignees are shown on 2D map.The results demonstrated by taking the GlobalWafers as an example to formulate its R&D strategy, it is lack of patent at manufacturing apparatus, raw material manufacturing, and inspection method, and lack of function objective at melt level, crystallographic, and crucible improvement. These may be the points of breaking through technical barriers. It is good suggestion to increase the average number of independent claims and the ratio of PCT applications to improve the quality of international patent portfolios. The advice from patent technology strength analyses is that it needs to develop more advanced technology.

Adaptive design for Gaussian process regression under censoring

A key objective in engineering problems is to predict an unknown experimental surface over an input domain. In complex physical experiments this may be hampered by response censoring which results in a significant loss of information. For such problems, experimental design is paramount for maximizing predictive power using a small number of expensive experimental runs. To tackle this, we propose a novel adaptive design method, called the integrated censored mean-squared error (ICMSE) method. The ICMSE method first estimates the posterior probability of a new observation being censored, then adaptively chooses design points that minimize predictive uncertainty under censoring. Adopting a Gaussian process regression model with product correlation function, the proposed ICMSE criterion is easy to evaluate which allows for efficient design optimization. We demonstrate the effectiveness of the ICMSE design in two real-world applications on surgical planning and wafer manufacturing.

Crack damage control for diamond wire sawing of silicon: The selection of processing parameters

Fixed diamond wire sawing has been the most common technology to cut mono- and multi-crystalline silicon into wafers in the fields of photovoltaics and integrated circuits. The crack damage inevitably occurred in wire sawing is preventing the further reduction of wafer manufacturing cost due to wafer breakage and subsequent crack damage removal. This paper presents a numerical model to predict the processing parameters for a given expected crack damage depth of as-cut wafers, aiming to realize the control of crack damage. The model adopts a classic median-and-lateral crack system to describe the crack damage induced by the scratching of diamond abrasives randomly distributed on wire. The key processing parameter - the ratio of feed speed to wire speed - is determined by making the calculated crack damage depth equal to the expected value. The deflection/bow angle of wire is checked to avoid excessive end-cutting time and severe shape deviation of wafers. The established model is verified by wire sawing experiments using the processing parameters predicted by this model. The maximum relative error between experimental values and expected values of the crack damage depth is 5.26%. This model can be applied to the industrial crack damage control of as-cut wafers by the selection of processing parameters.

Surface Defect Classification in Silicon Wafer Manufacturing Using the Linear-Based Channeling and Rule-Based Binning Algorithms

Developing an accurate means of classifying defects, such as crystal-originated pits, surface-adhered foreign particles, and process-induced defects, using scanning surface inspection systems (SSIS) is of paramount importance because it provides the opportunity to determine the root causes of defects, which is valuable for yield enhancement. This report presents a novel defect classification approach developed by optimizing the linear-based channeling (LBC) and rule-based binning (RBB) algorithms that are applied to a commercially available SSIS (KLA-SP5), in combination with test sample selection including the signature defect patterns associated with the typical crystal growth process. The experimental results demonstrate that defect classification is possible with an accuracy and purity above 80% using the LBC algorithm and 90% using the RBB algorithm.

Material-related fundamentals of cutting techniques for GaAs wafer manufacturing

Abstract Driven by the requirement of high cutting efficiency and improvement of wafer flatness, wire sawing of GaAs single crystals under brittle material removal conditions has been studied. Crack nucleation and crack propagation were investigated by indentation and scratching tests on polished {100}-oriented semi-insulating GaAs wafers. Based on these results a concept has been developed that allows to control the force balance in the cutting slits so that the deflection of the wires perpendicular to the cutting planes is minimal resulting in cuts of high flatness. The concept has been successfully introduced in mass production of GaAs wafers.

Mueller Matrix Ellipsometric Characterization of Nanoscale Subsurface Damage of 4H-SiC Wafers: From Grinding to CMP

Subsurface damage of 4H-silicon carbide (SiC) wafers, which is detrimental to the performance and lifetime of SiC-based photoelectric devices, is easily induced during surface machining process due to their particular mechanical and physical properties. A nondestructive and effective characterization technique is essential for high quality products in the wafer manufacturing process. A method based on the Mueller Matrix Spectroscopic Ellipsometry (MMSE) is proposed to detect the nanoscale subsurface damage of 4H-SiC wafers induced by grinding and polishing. The Mueller matrix elements which are sensitive to the damage information have been identified through both simulation and experiment. The damage layer and its roughness are considered in optical modeling at different processing stages. The results show that both the surface texture and the damage layer contribute to the Mueller matrix values. The fitting thickness of the damage layer is consistent with the value from transmission electron microscope (TEM); the refractive index of the damage layer matches the surface elements analysis result from X-ray photoelectron spectroscopy (XPS). The results suggest that the MMSE-based method could offer a promising nondestructive method to detect global wafer subsurface damage and its evolution during grinding and polishing, which eventually could benefit process optimization in the whole wafer manufacturing process.

An Investigation of Edge Bead Removal Width Variability, Effects and Process Control in Photolithographic Manufacturing

We present a low-cost, vision-based method to study the effects of photo resist edge bead removal (EBR) width variability in a manufacturing environment. In micro- and nanofabrication manufacturing wafer edge regions are frequently out of sight and less studied due to their non-yielding attributes. However, they might significantly influence product quality (delamination) and equipment health (contamination). The proposed method utilizes partial wafer edge inspection and open-source image processing to measure the EBR widths without requiring prior image model training. The method is based on the computation of the offset between two local maxima (peaks) in the Hough parametric space equivalent of the Euclidean distance between wafer edge and EBR line. The proposed method is robust to imperfect removal line definitions and highly integrable in automation workflows for equipment health monitoring and statistical process control (SPC). An extensive 180-day survey of EBR width variability revealed low frequency but high severity events.

Recovery of linear components: Reduced complexity autoencoder designs

Reducing dimensionality is a key preprocessing step in many data analysis applications to address the negative effects of the curse of dimensionality and collinearity on model performance and computational complexity, to denoise the data or to reduce storage requirements. Moreover, in many applications it is desirable to reduce the input dimensions by choosing a subset of variables that best represents the entire set without any a priori information available. Unsupervised variable selection techniques provide a solution to this second problem. An autoencoder, if properly regularized, can solve both unsupervised dimensionality reduction and variable selection, but the training of large neural networks can be prohibitive in time sensitive applications. We present an approach called Recovery of Linear Components (RLC), which serves as a middle ground between linear and non-linear dimensionality reduction techniques, reducing autoencoder training times while enhancing performance over purely linear techniques. With the aid of synthetic and real world case studies, we show that the RLC, when compared with an autoencoder of similar complexity, shows higher accuracy, similar robustness to overfitting, and faster training times. Additionally, at the cost of a relatively small increase in computational complexity, RLC is shown to outperform the current state-of-the-art for a semiconductor manufacturing wafer measurement site optimization application.

CFD Analysis of the removal process of residual carbon

Recently, the need of renewable energy is significantly increasing by carbon neutral, the demand of silicon wafers is also increasing as a result of growth of the solar energy industry. However, the recycling technology of silicon sludge is needed because a large amount of waste silicon sludge is generated from the silicon wafer manufacturing process. Many researches have been studied to convert the silicon component contained in the silicon sludge to silicon carbide (SiC). SiC powder can be synthesized using silicon sludge by heat treatment with carbon addition. Therefore, the removal process of residual carbon is required because the excess carbon is generally used to maximize the SiC conversion rate. In this work, computational fluid dynamic (CFD) analysis of the removal process of residual carbon has been studied by using the commercial CFD code ANSYS FLUENT.

Nano−Micro Characterization of Defects on Silicon Surfaces: An Industrial Perspective of Metrology Challenges

The electronic device industry is known to have been driven since its early stages by a continuous technological effort of miniaturization because of the dual need of manufacturing cost reduction through integration and offers to the user market of smaller electronic applications, more efficient, versatile, and differentiable. Silicon wafer manufacturers have been forced to provide larger size silicon wafers. 300 mm diameter is nowadays covering more than 50% of the total market, with dimension and density of residual defects moving from micrometers to nanometers, from ppt to ppq, or even less. In this context, the proper choice of measurement technique and setup which can guarantee measurement reliability to detect a given defect and provide information of its distribution inside the wafer is mandatory. It has to cope the need to control material quality in a range more frequently close to the measurement detection limit and improve the associated manufacturing process capabilities. Herein, a few examples in the area of crystallographic/morphological defects and chemical impurities on silicon wafers are proposed, reviewing the defect analysis approach inside a manufacturing environment. The discussion also involves the final product certification data reporting which tends to convey in a very synthetic format the whole measurement and control process.

Research on Wafer Surface Defect Pattern Detection Method Based on Incremental Learning

Wafer manufacturing is an important step in quality control and analysis in the semiconductor industry. The defect pattern classification algorithm of wafer maps has received extensive attention from academia and industry. At present, most methods for detecting wafer surface defect patterns focus on static data model classification and analysis. However, in the production process, static data models cannot satisfy the dynamic analysis of wafer defect patterns in the form of streaming data. In this regard, this paper proposes a wafer surface defect pattern detection method based on incremental learning. Our experiment uses Resnet as the backbone network, and the data set uses the WM811K wafer data set. Experiments have proved that our method can achieve better classification accuracy in the field of wafer defect detection, which provides the possibility for continuous learning of wafer defects in the future.

Research on Silicon Wafer Manufacturing Process and Physical Properties Testing Using High-Purity Polysilicon

The shape of a bare wafer is round, so it is called a wafer or a silicon wafer. It is the basis for the production of silicon semiconductor integrated circuits. The silicon wafer is cut from a large piece of semiconductor material silicon ingot. The high-purity polysilicon (its purity is up to 99.999999999%) is into a large single crystal, given the correct orientation and an appropriate amount of N-type or P-type doping, a silicon ingot is obtained through five-step crystal growth. Wafers (wafers) are then made from silicon ingots by more than eight processes. This paper investigates the single crystal silicon growth and wafer preparation process technology, and finally discusses the evolution of wafer size growth and changes in the development of the semiconductor industry chain.