Wafer Lots Research Articles

A comprehensive constraint programming approach for the rolling horizon-based scheduling of automated wet-etch stations

This contribution introduces a novel and comprehensive way of dealing with the automated wet-etch station (AWS) scheduling problem. It first analyzes the field and points out some very important problem aspects that have not been properly addressed yet. Then, an expressive constraint programming (CP) formulation that considers all types of AWS transfer device movements is proposed. The model accounts for both (i) loaded trips the robot makes to transfer wafer lots between consecutive baths, and (ii) empty movements that take place when the device moves itself from a bath, where it has dropped a wafer lot, to another bath where it is required to pick up a different lot. The CP approach is afterward generalized in order to implement an innovative rolling horizon methodology. The proposed method allows the continuous operation of the wet-etch station, minimizing the unproductive intervals that would otherwise appear between the scheduling periods that correspond to different wafer lot sets that are fed by the previous manufacturing step. The formulation has been extensively tested with problem instances of various dimensionalities in productivity maximization scenarios, in which makespan was chosen as the performance measure. The results have demonstrated that robot unloaded movements cannot be neglected; otherwise, they may lead to incorrect schedules. Furthermore, they have shown that AWS scheduling needs to be addressed as an on-line activity.

All-Digital PMOS and NMOS Process Variability Monitor Utilizing Shared Buffer Ring and Ring Oscillator

This paper proposes an all-digital process variability monitor based on a shared structure of a buffer ring and a ring oscillator. The proposed circuit monitors the PMOS and NMOS process variabilities independently according to a count number of a single pulse which propagates on the ring during the buffer ring mode, and an oscillation period during the ring oscillator mode. Using this shared-ring structure, we reduce the occupation area about 40% without loss of process variability monitoring properties compared with the conventional circuit. The proposed shared-ring circuit has been fabricated in 65nm CMOS process and the measurement results with two different wafer lots show the feasibility of the proposed process variability monitoring scheme.

An optimization-based framework for the scheduling of Automated Manufacturing Systems

Automated Wet-Etch Station (AWS) is a complex flow shop operation process in Semiconductor Manufacturing Systems. In this station, automated material-handling robots are used to move wafer lots across a lineal configuration of chemical and water baths. In every bath, limited processing times and complex storage policies must be assured. In this work, an optimization-based framework is developed to improve the operations of AWS. To do this, a sequential procedure based on mixed-integer linear programming (MILP) formulations is proposed. The aim of this work is to provide a robust approach to generate near-optimal results to industrial AWS scheduling problems with modest CPU time.

A novel optimization method to automated wet-etch station scheduling in semiconductor manufacturing systems

This work addresses the short-term scheduling of one of the most critical stages in the semiconductor industry, the automated wet-etch station (AWS). An efficient MILP-based computer-aided tool is developed in order to achieve a proper synchronization between the activities of sequential chemical and water baths and limited automated wafer's lot transfer devices. The major goal is to find the optimal integrated schedule that maximizes the whole process productivity without generating wafer contamination. Several examples are successfully solved to illustrate the capabilities of the proposed method.

Weighted Cost Rate-Based Heuristic Scheduling Method for Semiconductor Furnaces

In semiconductor wafer manufacturing, furnaces are mainly used for diffusion and deposition operations. During operations, wherever a furnace becomes available, scheduling the next batch deals with decisions on a batch which operation to process next and how many wafer lots to group the batch. To resolve the mentioned scheduling problem of the furnace where existing multi-products and different due dates, a heuristic dynamic scheduling algorithm called WCRHA (weighted cost rate heuristic algorithm) is presented to minimize the objective value of the waiting cost per unit time based on due date constraints. Simulation results show that the proposed algorithm is valid and feasible. Compared with the previous dynamic scheduling algorithms, it is more efficient in ensuring delivery and reducing completion time.

Silicon photonics manufacturing

Most demonstrations in silicon photonics are done with single devices that are targeted for use in future systems. One of the costs of operating multiple devices concurrently on a chip in a system application is the power needed to properly space resonant device frequencies on a system's frequency grid. We asses this power requirement by quantifying the source and impact of process induced resonant frequency variation for microdisk resonators across individual die, entire wafers and wafer lots for separate process runs. Additionally we introduce a new technique, utilizing the Transverse Electric (TE) and Transverse Magnetic (TM) modes in microdisks, to extract thickness and width variations across wafers and dice. Through our analysis we find that a standard six inch Silicon on Insulator (SOI) 0.35 μm process controls microdisk resonant frequencies for the TE fundamental resonances to within 1 THz across a wafer and 105 GHz within a single die. Based on demonstrated thermal tuner technology, a stable manufacturing process exhibiting this level of variation can limit the resonance trimming power per resonant device to 231 μW. Taken in conjunction with the power to compensate for thermal environmental variations, the expected power requirement to compensate for fabrication-induced non-uniformities is 17% of that total. This leads to the prediction that thermal tuning efficiency is likely to have the most dominant impact on the overall power budget of silicon photonics resonator technology.

Scheduling algorithms for a semiconductor probing facility

This paper focuses on a scheduling problem in a semiconductor wafer probing facility. In the probing facility, wafer lots with distinct ready times are processed on a series of workstations, each with identical parallel machines. We develop a heuristic algorithm for the problem with the objective of minimizing total tardiness of orders. The algorithm employs a bottleneck-focused scheduling method, in which a schedule at the bottleneck workstation is constructed first and then schedules for other workstations are constructed based on the schedule at the bottleneck. For scheduling wafer lots at the bottleneck workstation, we consider prospective tardiness of the lots as well as sequence-dependent setup times required between different types of wafer lots. We also present a rolling horizon method for implementation of the scheduling method on a dynamic situation. The suggested methods are evaluated through a series of computational experiments and results show that the methods work better than existing heuristic methods.

Scheduling Wafer Lots on Diffusion Machines in a Semiconductor Wafer Fabrication Facility

This paper focuses on the problem of scheduling wafer lots on diffusion workstations in a semiconductor wafer fabrication facility. In a diffusion workstation, there are multiple identical machines, and each of them can process a (limited) number of wafer lots at a time. Wafer lots can be classified into several product families, and wafer lots that belong to the same product family can be processed together as a batch. Processing times and setup times for wafer lots of the same product family are the same, but ready times of the wafer lots (at the diffusion workstation) may be different. We present several heuristic algorithms for the problem with the objective of minimizing total tardiness. For evaluation of performance of the suggested algorithms, a series of computational experiments is performed on randomly generated test problems. Results show that the suggested algorithms perform better than algorithms currently used in practice.

Cycle forecasting EWMA (CF-EWMA) approach for drift and fault in mixed-product run-to-run process

In semiconductor manufacturing processes, mixed-products are usually fabricated on the same set of process tool with different recipes. Run-to-run controllers which based on the exponential weighted moving average (EWMA) statistic are probably the most frequently used in industry for the quality control of certain semiconductor manufacturing process steps. However, for mixed-product drifted process, if the break length of a product is large, then the process output at the beginning runs of each cycle will far deviate from the target value which will lead to a possible high rework rate and lots of waste wafers. Therefore, this study aims to develop a new approach named cycle forecasting EWMA (CF-EWMA) approach to deal with the problem of large deviations in the first few runs of each cycle. Furthermore, a common fault, i.e., the step fault, is also considered in this paper, and fault tolerant cycle forecasting EWMA (FTCF-EWMA) approach is proposed. Simulation study shows that the proposed approaches are effective.

Determining the optimal probing lot size for the wafer probe operation in semiconductor manufacturing

In this study, we reformulated the problem of wafer probe operation in semiconductor manufacturing to consider a probe machine (PM) which has a discrete Weibull shift distribution with a nondecreasing failure rate. To maintain the imperfect PM during the probing of a lot of wafers, a minimal repair policy is introduced with type II inspection error. To increase the productivity of the PM, this paper aims to find an optimal probing lot size that minimizes the expected average processing time per wafer. Conditions and uniqueness for the optimal lot size are explored. The special case of a geometric shift distribution is studied to find a tighter upper bound on the optimal lot size than in previous study. Numerical examples are performed to evaluate the impacts of minimal repair on the optimal lot size. In addition, the adequacy of using a geometric shift distribution is examined when the actual shift distribution has an increasing failure rate.

Development of Barrier Slurry for Improved Electrical Performance

As device dimensions shrink to the sub-65 nm regime, a greater demand is placed upon the barrier polishing process. Therefore the ability to modulate the barrier chemical mechanical planarization performance window by process and formulation synergy can provide tunability at advanced technology nodes to meet stringent electrical, topography, and defect requirements. This study introduces one approach in achieving the synergy between barrier polishing slurry and the development of a robust process. The system investigated has demonstrated desirable uniformity control and greater margin for polishing. Extensive layer testing (more than 10 wafer lots) has consistently shown better within-wafer (resistance) spread compared to process of record, with improvement above 30% for all layers. The slurry also shows a more gradual fluctuation over a 20 s polish time range. A marathon run has also shown consistent polishing rate performance over the pad life with comparable defect density and characteristics.

Capacity requirements planning for twin Fabs of wafer fabrication

Based on the assumption of infinite capacity, a Capacity Requirements Planning System (CRPS) is developed for twin fabs of wafer fabrication. Several shared equipments exist only in one of the twin fabs linked by an Inter-Fab Material Handling System. CRPS consists of four major modules. WIP-Pulling Module pulls work-in-process (WIP) that is the closest to the end of the process route to meet the Master Production Schedule. Workload Accumulation Module then calculates the expected equipment loading in different time buckets. If WIP cannot meet the Master Production Schedule (MPS) requirement, new wafer lots need to be released. Wafer Release Time Module is used to determine the release time of new lots by evaluating their expected equipment loading at the twin fabs on various time buckets. According to the lot release time, Wafer Start Fab Module can be used to evaluate the expected loading for each of the twin fabs and determine the start fab to optimise the workload balance among these twin fabs on various days. Based on experimental design, simulation results show that CRPS can balance the equipment loading between the twin fabs with shared equipment, on various days, and across various equipments at various levels of demands.

A fuzzy back propagation network ensemble with example classification for lot output time prediction in a wafer fab

Lot output time prediction is a critical task to a wafer fabrication plant (wafer fab). To further enhance the accuracy of wafer lot output time prediction, the concept of clustering is applied to Chen’s fuzzy back propagation network (FBPN) approach in this study by pre-classifying wafer lots before predicting their output times with several FBPNs that have the same topology. Each wafer lot category has a corresponding FBPN that is applied to predict the output times of all lots belonging to the category. In choosing the learning examples of each category, whether a wafer lot can be unambiguously classified or not and the accuracy of predicting the output time of the lot are simultaneously taken into account. To validate the effectiveness of the proposed methodology and to make comparison with some existing approaches, the actual data in a wafer fab were collected. According to experimental results, the prediction accuracy of the proposed methodology was significantly better than those of some existing approaches in most cases by achieving a 19–52% (and an average of 38%) reduction in the root-mean-square-error (RMSE). On the other hand, compared with the fuzzy c-means (FCM)-BPN-ensemble approach, the performance of the proposed methodology in the efficiency respect was indeed improved.

A Due-Date-Based Algorithm for Lot-Order Assignment in a Semiconductor Wafer Fabrication Facility

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> This paper focuses on a lot-order assignment problem, called the pegging problem, in a semiconductor wafer fabrication facility. Pegging is a process of assigning wafer lots to orders for wafers. We consider two types of pegging strategies: hard pegging strategy, under which the lot-order assignment is not changed once lots are assigned to orders; and soft pegging strategy, under which the lot-order assignment can be changed during the production period. For the soft pegging strategy, we develop three operational policies and three algorithms for the pegging problem of assigning lots to orders with the objective of minimizing total tardiness of the orders. To evaluate performance of the suggested policies and algorithms, we perform simulation experiments using real factory data as well as randomly generated data sets. Results of the simulation tests show that the repegging policies and the algorithms operated under the soft pegging strategy give better results than the hard pegging strategy. </para>

A HEURISTIC SCHEDULING APPROACH TO THE DEDICATED MACHINE CONSTRAINT

The constraint of having a dedicated machine for the photolithography process in semiconductor manufacturing is a new challenge introduced in photolithography machinery due to natural bias. With dedicated machine constraint, the wafer lots passing through each photolithography process have to be processed by the same machine. The purpose of the limitation is to prevent the natural bias of the photolithography machine. However, much research proposed by previous researchers did not discuss the dedicated photolithography machine constraint. In this paper, we propose the Load Balancing (LB) scheduling approach based on a Resource Schedule and Execution Matrix (RSEM) framework to tackle the constraint. The proposed LB approach schedules each wafer lot at the first photolithography stage to a suitable machine according to the load factor of these photolithography machines. We describe the LB approach and the construction process of the RSEM framework. We also present an example to demonstrate our approach and simulation results to validate our approach.

Using an artificial neural network prediction model to optimize work-in-process inventory level for wafer fabrication

A proper selection of a work-in-process (WIP) inventory level has great impact onto the productivity of wafer fabrication processes, which can be properly used to trigger the decision of when to release specific wafer lots. However, the selection of an optimal WIP is always a tradeoff amongst the throughput rate, the cycle time and the standard deviation of the cycle time. This study focused on finding an optimal WIP value of wafer fabrication processes by developing an algorithm integrating an artificial neural network (ANN) and the sequential quadratic programming (SQP) method. With this approach, it offered an effective and systematic way to identify an optimal WIP level. Hence, the efficiency of finding the optimal WIP level was greatly improved.

A fuzzy-neural and multiple-bucket approach for estimating lot cycle time in a wafer fab with dynamic product mix

A fuzzy-neural and multiple-bucket approach is proposed in this study for lot cycle time estimation in a wafer fab with dynamic product mix, which was seldom thoroughly investigated in the past studies. The proposed methodology is composed of two parts. In the first part, the multiple-bucket approach is applied to consider the future release plan of the wafer fab. Subsequently, the FCM-FBPN approach is applied to estimate the cycle time of every lot in the wafer fab. The buckets obtained in the first part become additional inputs to the FBPN. In this way, the fluctuation in the product mix since the release of a wafer lot can be considered in estimating the cycle time of the wafer lot. According to experimental results, the estimation accuracy of the proposed methodology was significantly better than those of many existing approaches. Other findings include that a large number of buckets were beneficial to the estimation accuracy, and might not worsen the efficiency of the proposed methodology.

Multiple-objective scheduling and real-time dispatching for the semiconductor manufacturing system

Implementing efficient scheduling and dispatching policies is a critical means to gain competitiveness for modern semiconductor manufacturing systems. In contemporary global market, a successful semiconductor manufacturer has to excel in multiple performance indices, consequently qualified scheduling approaches should provide efficient and holistic management of wafer products, information and manufacturing resources and make adaptive decisions based on real-time processing status to reach an overall optimized system performance. To cope with this challenge, a timed extended object-oriented Petri nets (EOPNs) based multiple-objective scheduling and real-time dispatching approach is proposed in this paper. Four performance objectives pursued by semiconductor manufacturers are integrated into a priority-ranking algorithm that serves as the initial scheduling guidance, and then all wafer lots will be dynamically dispatched by the hybrid real-time dispatching control system. A set of simulation experiments validate the proposed multiple-objective scheduling and real-time dispatching algorithm may achieve satisfactory performances.

Minimizing total weighted tardiness on a batch-processing machine with incompatible job families and job ready times

Semiconductor wafer fabrication facilities (“wafer fabs”) strive to maximize on-time delivery performance for customer orders. Effectively scheduling jobs on critical or bottleneck equipment in the wafer fab can promote on-time deliveries. One type of critical fab equipment is a diffusion oven which processes multiple wafer lots (jobs) simultaneously in batches. We present a new polynomial time Batch Improvement Algorithm for scheduling a batch-processing machine to maximize on-time delivery performance (minimize total weighted tardiness) when job arrivals are dynamic. The proposed algorithm's performance is compared to previous research efforts under varying problem conditions. Experimental studies demonstrate the effectiveness of the Batch Improvement Algorithm.

The infrastructure of the timed EOPNs-based multiple-objective real-time scheduling system for 300 mm wafer fab

Modern semiconductor wafer fabrication systems are changing from 200 mm to 300 mm wafer processing, and with the dual promises of more chips per wafer and economy of scale, leading semiconductor manufacturers are attracted to developing and implementing 300 mm wafer fabs. However, in today's dynamic and competitive global market, a successful semiconductor manufacturer has to excel in multiple performance indices, such as manufacturing cycle time and on-time delivery, and simultaneously optimize these objectives to reach the best-compromised system achievement. To cope with this challenge, in this paper, the infrastructure of a timed EOPNs-based multiple-objective real-time scheduling system (MRSS) is proposed to tackle complex 300 mm wafer fabs. Four specific performance objectives pursued by contemporary semiconductor manufacturers are integrated into a priority-ranking algorithm, which can serve as the initial scheduling guidance, and then all wafer lots will be dynamically dispatched by the real-time state-dependent dispatching system. This dispatching control system is timed EOPN-based and adopts a heterarchical organization that leads to a better real-time performance and adaptability. As the foundation of real-time schedule, the timed EOPNs modelling approach is expounded in detail, and the prototype of the MRSS simulation system is also provided.