Abstract
Most demonstrations in silicon photonics are done with single devices that are targeted for use in future systems. One of the costs of operating multiple devices concurrently on a chip in a system application is the power needed to properly space resonant device frequencies on a system's frequency grid. We asses this power requirement by quantifying the source and impact of process induced resonant frequency variation for microdisk resonators across individual die, entire wafers and wafer lots for separate process runs. Additionally we introduce a new technique, utilizing the Transverse Electric (TE) and Transverse Magnetic (TM) modes in microdisks, to extract thickness and width variations across wafers and dice. Through our analysis we find that a standard six inch Silicon on Insulator (SOI) 0.35 μm process controls microdisk resonant frequencies for the TE fundamental resonances to within 1 THz across a wafer and 105 GHz within a single die. Based on demonstrated thermal tuner technology, a stable manufacturing process exhibiting this level of variation can limit the resonance trimming power per resonant device to 231 μW. Taken in conjunction with the power to compensate for thermal environmental variations, the expected power requirement to compensate for fabrication-induced non-uniformities is 17% of that total. This leads to the prediction that thermal tuning efficiency is likely to have the most dominant impact on the overall power budget of silicon photonics resonator technology.
Highlights
Future high-density chip-to-chip and high performance computing (HPC) interconnect communications power consumption and off chip bandwidth requirements will be extremely challenging or impossible to meet using electrical interconnects [1,2]
Recent demonstrations of silicon photonic technology have shown that wavelength division multiplexed (WDM), low energy, high bandwidth interconnect schemes are compatible with existing silicon high volume manufacturing (HVM) techniques in microelectronics even if high volume integration is still in its nascent stage [3,4,5]
In evaluating the power costs of systems built with demonstrated devices in silicon photonics, we evaluated a six inch Silicon on Insulator (SOI) 0.35μm process to quantify the frequency variation across runs, wafers and dice
Summary
Future high-density chip-to-chip and high performance computing (HPC) interconnect communications power consumption and off chip bandwidth requirements will be extremely challenging or impossible to meet using electrical interconnects [1,2]. While important in making modulation power insignificant, systems require many devices that are instead tuned to fixed laser frequencies. This integration costs power to orderly initialize and maintain each resonance on a grid of channels. We use a new technique to extract the contributors to the variation and use this information along with careful assumptions about future interconnect architecture and current HVM capabilities to make estimates of the total power consumption, including resonant frequency trimming and tuning, for future chip to chip silicon photonic links
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