Wafer Lots Research Articles

Development of Fault Detection Systems: The Hadoop Ecosystem Implementation

Semiconductor manufacturing relies on a long and complex production line for wafer fabrication. In a modern semiconductor fabrication plant (fab), a wafer manufacturing line is composed of more than 1,000 manufacturing tools and an overhead hoist system for delivering wafer lots among the tools. Novel technologies, such as Internet of Things (IoT) and software engineering technologies, are adopted in semiconductor manufacturing such that large amounts of data can be collected from manufacturing tools. Also, these tools and the overhead hoist system should cooperate well with each other. Due to the data-processing capacity limitation in a current fault detection and classification (FDC) system, the diagnosis efficiency is limited such that some undesired events cannot be detected in time, leading to significant economic loss. With the booming development of big data technology, this work conducts a study on a new FDC framework based on a Hadoop ecosystem to deal with the data-processing limitation and improve diagnosis efficiency. Also, a migration path is presented such that the current FDC system can be smoothly migrated to a Hadoop ecosystem-based one without shutting down a wafer fabrication line. Experimental results show that the proposed FDC framework can run safely and stably.

Fault Diagnosis of Wafer Acceptance Test and Chip Probing Between Front-End-of-Line and Back-End-of-Line Processes

With the rapid development of the semiconductor industry, fault diagnosis is an important task in routine operations to determine the root cause for faults that occur. A tool in manufacturing processes is equipped with a wide variety of sensors that record different types of process data. Wafers being processed are accompanied by a considerable amount of process data as a multivariate time series. Identifying the key process parameters and the corresponding process operations where faults occur can be used to facilitate the tasks of monitoring the process, maintaining the stability of the process, and stabilizing wafer production yield. This article proposes a novel solution procedure for fault diagnosis of wafer acceptance test (WAT) and chip probing (CP) using machine learning (ML). Based on the process flow of wafers and the corresponding process data, a sampling method, called synthetic minority oversampling technique (SMOTE), is first used to augment classification models with an imbalanced process dataset, and the best-practice SMOTE ratio is sought by using four competitive classifiers. By means of principal component analysis (PCA), the original data are transformed into visualizations to explore the distributions of good and bad lots of wafers. Based on the comparison of the four classifiers used in the test, the proposed logistic regression with data augmentation (LR-SMOTE) performs best. The ten most important features identified by using the LR are collected to determine potential failure operations. The identified failures in operations returned by using the proposed solution procedure for fault diagnosis of WAT and CP were confirmed by the engineers who work in the domain. Note to Practitioners—In semiconductor manufacturing practice, during the WAT and CP, domain engineers need to trace upstream the key process parameters and the corresponding key operations in the front-end-of-line (FEOL) process if any faults are detected in the back-end-of-line (BEOL) process. In fact, the FEOL and the BEOL are located in completely separate plants with different clean room standards. Bridging the information gap between these two different processes merits thorough scrutiny. Another challenge posed by fault diagnosis of WAT and CP is that the total number of features (i.e., process parameters) involved in the FEOL can be tens of thousands, leading to an adverse effect of data sparsity on model building.

Anticipatory transport system with hybrid linear and nonlinear forecasting using streaming wafer process data

In semiconductor plants, autonomous vehicle systems (AVSs) are designed to transfer wafer lots using several hundreds of vehicles. To minimize the idleness of production machines, vehicles must be quickly assigned and sent to the required location in advance. Currently, owing to uncertainties that exit in production processing, simple deterministic heuristic approaches are the ones that are predominantly used when making decisions regarding lot discharging and recharging of production machines. However, to obtain better solutions that reflect the near-future states of production machines and AVSs, more sophisticated approaches are required. To address this, we propose a hybrid predictive algorithm using which a delivery vehicle can be sent in advance to minimize the production machine idle time. To predict the remaining processing time, we combine a latent variable regression and an artificial neural network to model and generalize the linear and the nonlinear patterns of wafer takt times. We then use dynamic time warping to identify the best matching pattern for the wafers being processed, thereby accurately estimating the remaining processing time. The experimental results demonstrated the superior performance of the proposed method in comparison to the existing ones in terms of accuracy. Finally, based on the results of field applications, we found that the proposed method can improve the operational efficiency of AVSs by allowing fast wafer transfer and maximize production throughput by reducing machine idle time.

Storage prioritization by redistributing wafer lot transfers to enhance real-world fab throughput

Storage prioritization by redistributing wafer lot transfers to enhance real-world fab throughput

Wafer Lot Assignment for Parallel-Producing Tools Based on Heuristic Clustering Algorithm

Beyond the widely-studied scheduling of wafers within cluster tools, a novel and important perspective is raised in this paper to tackle an upper-level optimization problem in real-world production, i.e., the assignment of hybrid types of wafer lots to a set of cluster tools with parallel modules to minimize the maximum completion time for the lots. The main difficulty in addressing such a problem is that the objective, i.e., the maximum completion time, cannot be calculated explicitly beforehand. To make this problem tractable, the associated maximal overlap among tools is utilized to heuristically evaluate the objective for the problem. Besides, since the cluster tools for processing are identical, we further tackle this problem as a clustering issue. Accordingly, a clustering algorithm based on greedy searching is proposed to allocate wafer lots into cluster tools while minimizing the maximal overlap. To elucidate our method and its significance in real-world production, the wet bench tool in wet cleaning process is taken as a case study. We compare the proposed algorithm with the empirical method in fabs and several intelligent optimization algorithms, and the experimental results verify the effectiveness of our proposed method in terms of improved efficiency.

A fuzzy deep predictive analytics approach for enhancing cycle time range estimation precision in wafer fabrication

The cycle time of a wafer lot refers to the time that the wafer lot has experienced from its input to output. Predicting the cycle time of each wafer lot is a crucial task for a wafer fabrication factory (wafer fab), but existing prediction methods cannot achieve 100% accuracy. Therefore, if the range of the cycle time can be estimated, it will be of great reference value. For this purpose, this research proposes a fuzzy deep predictive analytics approach. In the proposed methodology, first, decision variables related to the cycle time of a wafer lot are inputted into a deep neural network to predict the cycle time. Then, the parameters of the deep neural network are fuzzified according to an incremental fuzzification mechanism to estimate the range of the cycle time. Compared with existing methods, the proposed methodology fuzzifies more network parameters to further tighten the ranges of fuzzy cycle time forecasts. Experimental results showed that the proposed methodology improved the estimation precision in terms of the average range by approximately 80%.

A fuzzy hierarchical reinforcement learning based scheduling method for semiconductor wafer manufacturing systems

Scheduling semiconductor wafer manufacturing systems has been viewed as one of the most challenging optimization problems owing to the complicated constraints, and dynamic system environment. This paper proposes a fuzzy hierarchical reinforcement learning (FHRL) approach to schedule a SWFS, which controls the cycle time (CT) of each wafer lot to improve on-time delivery by adjusting the priority of each wafer lot. To cope with the layer correlation and wafer correlation of CT due to the re-entrant process constraint, a hierarchical model is presented with a recurrent reinforcement learning (RL) unit in each layer to control the corresponding sub-CT of each integrated circuit layer. In each RL unit, a fuzzy reward calculator is designed to reduce the impact of uncertainty of expected finishing time caused by the rematching of a lot to a delivery batch. The results demonstrate that the mean deviation (MD) between the actual and expected completion time of wafer lots under the scheduling of the FHRL approach is only about 30 % of the compared methods in the whole SWFS.

Hierarchical Transfer Learning for Cycle Time Forecasting for Semiconductor Wafer Lot under Different Work in Process Levels

The accurate cycle time (CT) prediction of the wafer fabrication remains a tough task, as the system level of work in process (WIP) is fluctuant. Aiming to construct one unified CT forecasting model under dynamic WIP levels, this paper proposes a transfer learning method for finetuning the predicted neural network hierarchically. First, a two-dimensional (2D) convolutional neural network was constructed to predict the CT under a primary WIP level with the input of spatial-temporal characteristics by reorganizing the input parameters. Then, to predict the CT under another WIP level, a hierarchical optimization transfer learning strategy was designed to finetune the prediction model so as to improve the accuracy of the CT forecasting. The experimental results demonstrated that the hierarchically transfer learning approach outperforms the compared methods in the CT forecasting with the fluctuation of WIP levels.

Investigation of the Impact of Neutron Irradiation on SiC Power MOSFETs Lifetime by Reliability Tests

High temperature reverse-bias (HTRB), High temperature gate-bias (HTGB) tests and electrical DC characterization were performed on planar-SiC power MOSFETs which survived to accelerated neutron irradiation tests carried out at ChipIr-ISIS (Didcot, UK) facility, with terrestrial neutrons. The neutron test campaigns on the SiC power MOSFETs (manufactered by ST) were conducted on the same wafer lot devices by STMicroelectronics and Airbus, with different neutron tester systems. HTGB and HTRB tests, which characterise gate-oxide integrity and junction robustness, show no difference between the non irradiated devices and those which survived to the neutron irradiation tests, with neutron fluence up to 10 (n/cm). Electrical characterization performed pre and post-irradiation on different part number of power devices (Si, SiC MOSFETs and IGBTs) which survived to neutron irradiation tests does not show alteration of the data-sheet electrical parameters due to neutron interaction with the device.

Production Flow Analysis in a Semiconductor Fab Using Machine Learning Techniques

In a semiconductor fab, wafer lots are processed in complex sequences with re-entrants and parallel machines. It is necessary to ensure smooth wafer lot flows by detecting potential disturbances in a real-time fashion to satisfy the wafer lots’ demands. This study aims to identify production factors that significantly affect the system’s throughput level and find the best prediction model. The contributions of this study are as follows: (1) this is the first study that applies machine learning techniques to identify important real-time factors that influence throughput in a semiconductor fab; (2) this study develops a test bed in the Anylogic software environment, based on the Intel minifab layout; and (3) this study proposes a data collection scheme for the production control mechanism. As a result, four models (adaptive boosting, gradient boosting, random forest, decision tree) with the best accuracies are selected, and a scheme to reduce the input data types considered in the models is also proposed. After the reduction, the accuracy of each selected model was more than 97.82%. It was found that data related to the machines’ total idle times, processing steps, and machine E have notable influences on the throughput prediction.

A Realizable Overlay Virtual Metrology System in Semiconductor Manufacturing: Proposal, Challenges and Future Perspective

Integrated circuits (IC) are fabricated on a wafer through stacked layers of circuit patterns. To ensure proper functionality, the overlay of each pattern layer must be within the tolerance. Inspecting each wafer’s overlay is unrealistic and impractical. Hence, wafers are selectively inspected at metrology stations through sampling strategies. With virtual metrology (VM), the metrology quality of the uninspected wafers can be estimated. Motivated by a real-world production environment of a 200mm semiconductor manufacturing plant (fab), a VM to estimate the overlay of the photolithography process is envisioned. Past researches on overlay VM leveraged fault detection and classification (FDC) data to estimate the overlay errors. As such, for fabs in the progress of completing their FDC development for photolithography equipment, a different modeling approach is required to realize an overlay VM that sustains the production line until FDC data can be leveraged for VM. With practical gaps that must be addressed in real fabs, this paper focuses on realizing an overlay VM for the photolithography process without leveraging FDC data. Therefore, the objectives of this paper are two folds: First, to identify the research challenges towards realizing the overlay VM. Second, to propose the future research perspectives of the envisioned overlay VM. Based on the future research perspectives, a two-steps overlay VM modeling approach utilizing data mining techniques is proposed toward realizing the envisioned overlay VM system. The proposed approach first classifies the process stability at the wafer lot level, and subsequently, performs overlay error estimations for wafers in the wafer lots classified with stable process. Linear regression models are proposed to perform overlay error estimations in this work to augment the interpretability of the overlay VM.

Practical Queueing Models for Preventive Maintenance Plan Optimization: Multiple Maintenance Types and Numerical Studies

Preventive Maintenance (PM) activities in semiconductor manufacturing are important for equipment availability and reliability. Since PMs are down events that remove a tool from service, when to conduct a PM and how to group multiple PM tasks into shared PM events are key issues. In this article, multiple types of PMs with different intervals are considered in G/G/m failure-prone queueing systems. PMs are classified into two categories: time-based preemptive and time-based non-preemptive. For each category of PM, this article provides PM planning optimization models to seek optimal PM intervals that minimize the mean cycle time of wafer lots. Simulation studies are conducted to explore the performance of the optimization model and the mean cycle time approximations. Moreover, sensitivity analysis is conducted and reveals several properties of the PM planning model. Implementation results are briefly reported for a toolset in semiconductor manufacturing that achieved a 12% reduction in mean cycle time using PM plans based on these modelling approaches.

Efficient Approach to Scheduling of Transient Processes for Time-Constrained Single-Arm Cluster Tools With Parallel Chambers

In wafer manufacturing, extensive research on the operations of cluster tools under the steady state has been reported. However, with the shrinking down of wafer lot size, such tools are frequently required to switch from handling one lot of wafers to another, resulting in more transient processes, including start-up and close-down ones. Also, wafer residency time constraint is critical for many wafer fabrication processes. To cope with the transient scheduling problem of time-constrained single-arm cluster tools with parallel chambers, based on a generalized backward strategy, this paper first builds timed Petri net models for these two transient processes. Then, two linear programs are derived for the first time to search a feasible schedule with a minimal makespan. Two industrial examples are given to demonstrate the effectiveness of the obtained results at last.

Simulation-Based Analysis on Operational Control of Batch Processors in Wafer Fabrication

In semiconductor wafer fabrication (wafer fab), wafers go through hundreds of process steps on a variety of processing machines for electrical circuit building operations. One of the special features in the wafer fabs is that there exist batch processors (BPs) where several wafer lots are processed at the same time as a batch. The batch processors have a significant influence on system performance because the repetitive batching and de-batching activities in a reentrant product flow system lead to non-smooth product flows with high variability. Existing research on the BP control problems has mostly focused on the local performance, such as waiting time at the BP stations. This paper attempts to examine how much BP control policies affect the system-wide behavior of the wafer fabs. A simulation model is constructed with which experiments are performed to analyze the performance of BP control rules under various production environments. Some meaningful insights on BP control decisions are identified through simulation results.

Capacity allocation with lot splitting in photolithography area using hybrid genetic algorithm based on self-tuning strategy

In the semiconductor industry with complicated manufacturing processes, a wafer lot passes through hundreds of operations, and the procedure takes a few months to complete. To meet customer deadline, utilizing and allocating machine capacity in a photolithography area efficiently by making suitable lot/order splitting decisions is a critical issue. Therefore, this research initially presents a mixed-integer nonlinear programming model to solve the capacity allocation problem with lot splitting in the photolithography area. Considering various manufacturing restrictions, such as process capability, machine dedication, and reticle constraints, this model can simultaneously determine the optimal lot-splitting and lot-allocation decisions to minimize the loading difference between each machine. Given the complexity of the mathematical model, this research further develops an adaptive hybrid genetic algorithm (HGA) with a local search mechanism and an auto-tuning strategy, namely, fuzzy logic controller, to solve the capacity allocation problem with lot splitting effectively. Finally, numerical experiments are conducted to demonstrate the efficiency of the developed HGA.

Big data analytics for cycle time related feature selection in the semiconductor wafer fabrication system

The dynamic wafer workshop gives rise to strong fluctuations of cycle time (CT) followed by earliness or tardiness penalty. Comprehending these fluctuations is a major challenge as the cycle time intricately interacts with massive parameters. This paper proposes a big data analytics method for feature selection to obtain all explanatory factors of CT that would shed light on the fluctuation of CT. Firstly, the correlative analysis is performed between each two candidate factors with mutual information metric to construct the observed network. Secondly, the network deconvolution is investigated to infer the direct dependence between the candidate factor and the CT by removing the effects of transitive relationships from the network. Additionally, a factor selection algorithm is designed to reduce the dimension of candidate factors to form the CT explanatory network, which contains the key factors interacting with the CT of wafer lots. The experimental results demonstrate the proposed method outperforms the references in term of classification and prediction accuracy. A case study is conducted with real data from a semiconductor wafer fabrication system, the big data captured for feature selection is analyzed, and the identified key factors are proved to be effective in forecasting and fluctuation interpretation of CT.

Scheduling Dual-Armed Cluster Tools for Concurrent Processing of Multiple Wafer Types With Identical Job Flows

As the order size for modern fabs tends to be smaller, fabs wish to process a class of similar wafer lots at a tool concurrently to reduce the work-in-progress lots as well as the total manufacturing lead time. We examine a scheduling problem for a dual-armed cluster tool that simultaneously produces multiple wafer types with identical wafer flow patterns but different process times. We prove that the conventional swap sequence, which is optimal and prevalently being used for single-wafer-type processing, is also optimal for such concurrent processing. We then propose a way of determining a release sequence of wafer types into the tool, called cycle plan , that maximizes the utilization of parallel chambers and hence increases the tool throughput rate. We present conditions for which the parallel chambers are shared by all wafer types and their workloads are evenly balanced so as to maximize the throughput rate. We also report the experimental results. Note to Practitioners —This paper suggests how to operate cluster tools for concurrent processing of similar wafer types. The results ensure that the conventional swap sequence is still effective for concurrent processing. We also provide a simple strategy of mixing different wafer types and the optimal release sequence for the wafers. We confirm that the tool throughput can be significantly improved when the release sequence of wafers is properly determined.

Ultrasonic Wake-Up With Precharged Transducers

We present an ultralow-power millimeter-sized ultrasonic wake-up receiver (WuRx) that uses precharged ultrasonic transducers to wirelessly receive wake-up signatures. Our WuRx takes advantage of the low carrier frequency afforded by the low speed of sound to achieve high impedance, and thus high sensitivity, operation in a millimeter-sized form factor. We discuss the system-level considerations that arise from the use of ultrasound as a mode of signature transmission, including the choice of operating frequency and the effect of transducer miniaturization on WuRx sensitivity. We describe the design of the receiver electronics and support our case for ultrasonic wake-up with thorough wireless measurements of error rate and electrical characterization of multiple dice from the same wafer lot. The receiver electronics are fabricated in 65-nm CMOS technology, while the receiver transducer is fabricated by means of a custom in-house process. The receiver achieves a sensitivity of −59.7 dBm at a bit error rate (BER) of 10−3 with a power consumption of 8 nW and a footprint of 14.5 mm2. Our benchmarking shows that the proposed WuRx achieves the lowest system area/aperture of all RF and acoustic WuRxs in the literature (1.45 $\times $ smaller than the state of the art) while maintaining competitive sensitivity and power consumption.

Closed-Form Expressions on Lot Completion Time for Dual-Armed Cluster Tools With Parallel Processing Modules

Cluster tools, which consist of processing modules (PMs) and a transport robot, are used for wafer fabrication processes in semiconductor manufacturing fabs. Once processing of a wafer lot containing several wafers is completed in a tool, an overhead hoist transport (OHT) unloads the lot and transports it to another tool. Since it is not easy to estimate when a wafer lot is completed, an OHT is required to wait for the wafer lot to be completed near the tool, or tools become idle due to the late delivery of wafer lots. To reduce the resulting idle time, a closed-form expression of the lot completion time is derived, especially, for a dual-armed cluster tool consisting of parallel PMs, to reflect real applications. We even consider lot switching operations where two consecutive wafer lots are processed with an overlap in analyzing the completion time. We finally show that the formulas derived can be used when there are small processing time variations experimentally. Note to Practitioners —For a dual-armed cluster tool with parallel processing modules (PMs), a closed-form expression on the lot completion time is derived. For this, we also consider lot switching operations, where the previous and next lots are temporarily processed together in a tool. With the formulas, we can send overhead hoist transports (OHTs) just-in-time to tools to unload or load wafer lots in tools, which can significantly reduce the idle time of tools and OHTs. In addition, the formulas can be used to design the number of PMs for wafer lots and assign wafer lots to tools to reduce their flow time. We believe that more efficient planning and scheduling in semiconductor manufacturing can be achieved by utilizing our results.

Simulation Study for Semiconductor Manufacturing System: Dispatching Policies for a Wafer Test Facility

The manufacture of semiconductor products requires many dedicated steps, and these steps can be grouped into several major phases. One of the major steps found at the end of the wafer fabrication process is the electrical die sorting (EDS) test operation. This paper focuses on dispatching policies in an EDS test facility to reduce unnecessary work for the system. This allows the semiconductor manufacturing facility to achieve better overall efficiency, thereby contributing to sustainable manufacturing by reducing material movements, the use of testing machines, energy consumption, and so on. In the facility, wafer lots are processed on a series of workstations (cells), and the facility holds identical parallel machines. The wafers are moved by an automatic material handling system from cell to cell as well as within cells. We propose several scheduling policies consisting of intercell and intracell material movements for efficient system operation. For this, four intercell scheduling policies and two intracell scheduling policies are introduced, and the effects of combinations are tested and evaluated through simulation experiments to obtain performance measures such as cycle time and work in process. The most efficient results among the combinations are presented as a proposed scheduling policy for a given EDS test facility.