Wafer Level Research Articles

Recent Developments in Low Temperature Wafer Level Metal Bonding for Heterogenous Integration

Abstract An overview of various low-temperature (<200°C) wafer bonding processes using metal interlayers is presented. Such processes are very attractive for novel applications in 3D heterogenous packaging as the allow for simultaneous formation of electrical interconnects, as well as hermetic encapsulation of various sensors and microelectromechanical systems-based devices. Metal wafer bonding is a generic category of processes consisting of various sub-categories, each one defined by the different principles governing the process. One can differentiate between eutectic wafer bonding (a eutectic alloy is formed as bonding layer during the process by liquid-solid interdiffusion), intermetallic wafer bonding (an intermetallic alloy is formed as bonding layer during the process by solid-liquid interdiffusion, a process known also as solid liquid intermetallic diffusion transient liquid phase, and metal thermo-compression wafer bonding. Different critical/gating parameters were investigated and their impact for generally reducing processing temperatures for the different metal bonding systems was studied.

Controlled Fabrication of Wafer-Scale, Flexible Ag-TiO2 Nanoparticle-Film Hybrid Surface-Enhanced Raman Scattering Substrates for Sub-Micrometer Plastics Detection.

As an important trace molecular detection technique, surface-enhanced Raman scattering (SERS) has been extensively investigated, while the realization of simple, low-cost, and controllable fabrication of wafer-scale, flexible SERS-active substrates remains challenging. Here, we report a facile, low-cost strategy for fabricating wafer-scale SERS substrates based on Ag-TiO2 nanoparticle-film hybrids by combining dip-coating and UV light array photo-deposition. The results show that a centimeter-scale Ag nanoparticle (AgNP) film (~20 cm × 20 cm) could be uniformly photo-deposited on both non-flexible and flexible TiO2 substrates, with a relative standard deviation in particle size of only 5.63%. The large-scale AgNP/TiO2 hybrids working as SERS substrates show high sensitivity and good uniformity at both the micron and wafer levels, as evidenced by scanning electron microscopy and Raman measurements. In situ bending and tensile experiments demonstrate that the as-prepared flexible AgNP/TiO2 SERS substrate is mechanically robust, exhibiting stable SERS activity even in a large bending state as well as after more than 200 tensile cycles. Moreover, the flexible AgNP/TiO2 SERS substrates show excellent performance in detecting sub-micrometer-sized plastics (≤1 μm) and low-concentration organic pollutants on complex surfaces. Overall, this study provides a simple path toward wafer-scale, flexible SERS substrate fabrication, which is a big step for practical applications of the SERS technique.

Biomimetic Contact Behavior Inspired Tactile Sensing Array with Programmable Microdomes Pattern by Scalable and Consistent Fabrication.

Flexible sensor arrays have attracted extensive attention in human-computer interaction. However, realizing high-performance sensor units with programmable properties, and expanding them to multi-pixel flexible arrays to maintain high sensing consistency is still struggling. Inspired by the contact behavior of octopus antenna, this paper proposes a programmable multistage dome structure-based flexible sensing array with robust sensing stability and high array consistency. The biomimetic multistage dome structure is pressurized to gradually contact the electrode to achieve high sensitivity and a large pressure range. By adjusting the arrangement of the multistage dome structure, the pressure range and sensitivity can be customized. More importantly, this biomimetic structure can be expanded to a multi-pixel sensor array at the wafer level with high consistency through scalable and high-precision imprinting technologies. In the imprinting process, the conductive layer is conformally embedded into the multistage dome structure to improve the stability (maintain stability over 22000 cycles). In addition, the braced isolation structure is designed to effectively improve the anti-crosstalk performance of the sensor array (crosstalk coefficient: 26.62dB). Benefitting from the programmable structural design and high-precision manufacturing process, the sensor array can be customized and is demonstrated to detect human musculation in medical rehabilitation applications.

Design Optimization and Reliability Evaluation in 1.2 kV SiC Trench MOSFET with Deep P Structure

In this paper, 1.2 kV SiC trench MOSFET with deep P structure has been proposed to effectively shield the trench bottom oxide. The various design splits, such as N concentration between deep P and deep P to trench distance, were experimentally evaluated and TCAD simulations were performed to extract maximum oxide electric field at trench bottom. Based on trade off results, critical design parameters were optimized to obtain low Rdson and stable breakdown voltage with acceptable oxide electric field. To evaluate trench gate oxide reliability in wafer level, gate oxide integrity (GOI/Vramp), charge to breakdown (QBD), and time dependent dielectric breakdown (TDDB) tests were conducted. Also, high temperature gate bias (HTGB) and high temperature reverse bias (HTRB) stress tests were carried out for assembled samples to compare device reliability depending on different designs. For the target design, the promising reliability results were confirmed in both wafer level and assembled samples.

Grating Coupler Design for Low-Cost Fabrication in Amorphous Silicon Photonic Integrated Circuits

Photonic circuits find applications in biomedicine, manufacturing, quantum computing and communications. Photonic waveguides are crucial components, typically having cross-section orders of magnitude inferior when compared with other photonic components (e.g., optical fibers, light sources and photodetectors). Several light-coupling methods exist, consisting of either on-plane (e.g., adiabatic and end-fire coupling) or off-plane methods (e.g., grating and vertical couplers). The grating coupler is a versatile light-transference technique which can be tested at wafer level, not requiring specific fiber terminations or additional optical components, like lenses, polarizers or prisms. This study focuses on fully-etched grating couplers without a bottom reflector, made from hydrogenated amorphous silicon (a-Si:H), deposited over a silica substrate. Different coupler designs were tested, and of these we highlight two: the superimposition of two lithographic masks with different periods and an offset between them to create a random distribution and a technique based on the quadratic refractive-index variation along the device’s length. Results were obtained by 2D-FDTD simulation. The designed grating couplers achieve coupling efficiencies for the TE-like mode over −8 dB (mask overlap) and −3 dB (quadratic variation), at a wavelength of 1550 nm. The coupling scheme considers a 220 nm a-Si:H waveguide and an SMF-28 optical fiber.

(Invited) Chemical Mechanical Planarization Integrated Data Collaboration: Uncover Hidden Interactions for Predictive Maintenance and PCN

This article introduces an innovative analytical methodology that employs machine learning to optimize and predict consumable impacts for Chemical Mechanical Planarization (CMP). By harnessing fleet CMP equipment performance and individual equipment characteristics, our proposed approach aims to elevate wafer-level quality, maximize equipment utilization rates, and minimize unnecessary downtime. CMP, a multifaceted process, its performance is often influenced by strong interactions from its critical components including slurry, pad, machine recipe, and dresser usage. This requires control beyond hardware advancements, especially when equipment is pushed to its limits. Therefore, the demand for higher precision on-wafer performance mandates a data collaboration with sophisticated analytical strategy. In addition, a digitalized product change notification (PCN) concept is also introduced to demonstrate effectiveness of applying integrated data analytics collaboratively across semiconductor chain to accelerate material manufacturing process changes, minimizing impacts on wafer results and shortening the learning cycle and ramp time to full production.Our study leverages data analytics to explore differences between equipment within the same fleet of similar processing. Engineers can deploy a process based on the historical performance of specific equipment, supported by a model trained on data from the same fleet. Furthermore, our approach enables each equipment to predict its own fingerprinted consumable maintenance, accurately forecasting the maintenance time for consumable changes. This concept is equally applicable for consumable PCN migrations.The first use case is to demonstrate the use of integrated data for fleet matching of CMP equipment and/or consumable batches running similar processes. This is particularly crucial as the demand for process precision increases and the need to reduce post-CMP result variability in removal rates and wafer-level uniformity intensifies. This approach could add proactive data driven strategy for process engineers who traditionally concentrate on the removal rate, a highly influential factor, with the standard deviation of platen and machine data identified as a key parameter.The second use case employs heatmaps analysis and proposes scatter plots as an intuitive method to comprehend intricate connections between average removal rates and various parameters. Machine learning is particularly advantageous in this context, as no single parameter plays a dominant role. Preliminary observations suggested, for example that dresser and pad characteristics may have compounding impacts to the wafer level performance.In summary, this article provides a roadmap for in-depth CMP data analysis fed into machine learning, aiming to unravel trends and influential factors that can enhance process optimization and shorten the PCN qualification timeline to meet the increasing demands for CMP process precision and efficiency in High Volume Manufacturing (HVM).

A Review on CMP Challenges in HWB and Wafer Level Packaging

Chemical mechanical planarization/polishing process faces new challenges in multiple new dimensions as hybrid wafer bonding (HWB) and flip-chip technologies evolve to enable innovative integration forms in semiconductor applications. The advanced capabilities of (i) manufacturing the CMOS independent of the memory array through HWB and, (ii) selecting the fully functional chiplets at the die level for heterogenous components for flip-chip bonding, drive cost-effective and high-performance integration.This paper is a review of the CMP challenges as these new technologies demand additional capabilities such as bonding surface planarization in addition to TSV exposure and polishing ability for backside metallization, edge trimming as well as backside thinning. The toolsets and current capabilities are reviewed in addition to the forthcoming trends of manufacturing ultrathin wafers.

Integrated Couplers of THz Radiation for Helical Slow-Wave Structures.

We have designed an integrated device that couples input and output coaxial horn antennas with a self-assembled helical slow-wave structure cradled in a v-groove on a silicon-on-insulator wafer. These devices will potentially enable the characterization of cold parameters and beam-wave interaction in slow-wave structures on a wafer level, i.e., without having to dice and package individual devices. In addition, such vertically integrated antennas and helical slow-wave structures may form the basis of compact and low-cost traveling-wave tube amplifiers operating at THz frequencies.

A MEMS resonant vacuum gauge for high vacuum measurement

In this paper, a MEMS resonant vacuum gauge (MRVG) based on the squeezed film damping is proposed and its theoretical measurement model is established. The sensitive structure and electrodes of the MRVG were fabricated on SOI wafers and were wafer level packaged including intake hole. An resonance excitation and capacitive detection circuit consists of capacitive voltage converter (C/V) module, PLL and modulation and demodulation module was designed. Experimental tests were carried out in a standard vacuum calibration chamber, and the measurement results verified the theoretical model. The indication accuracy of the MRVG is less than ±20% in the vacuum range of 9×10−5 Pa ∼ 1 Pa. Moreover, the output voltage is still not saturated at the highest vacuum level (9×10−5 Pa), which lays the foundation for subsequent measurement of higher vacuum levels.

Towards a CMOS compatible refractive index sensor: cointegration of TiN nanohole arrays and Ge photodetectors in a 200 mm wafer silicon technology

In this work, we present the monolithic integration of a TiN nanohole array and a Ge photodetector towards a CMOS compatible fabrication of a refractive index sensor in a 200 mm wafer silicon technology. We developed a technology process that enables fabrication with high yields of around 90%. Ge photodetectors with a Ge layer thickness of 450 nm and an area of 1600 µm2 (40 µm x 40 µm) show dark current densities of around 129 mA/cm2 and responsivities of 0.114 A/W measured by top illumination (TE polarization; λ = 1310 nm; angle of incidence = 14 °) at a reverse bias of 1 V. Nanohole arrays were structured in a 150 nm thick TiN layer. They were integrated into the back end of line and placed spatially close to the Ge photodetectors. After the metallization, passivation, and pad opening, the nanohole arrays were released with the help of an amorphous silicon stop layer. A significant impact of the TiN nanohole arrays on the optical behavior of the photodetector could be proven on the wafer level. Photocurrent measurements by top illumination confirm a strong dependence of optical properties on the polarization of the incident light and the nanohole array design. We demonstrate very stable photocurrents on the wafer level with a standard deviation of σ < 6%.

Wafer Level Vacuum Packaging of MEMS-Based Uncooled Infrared Sensors.

This paper introduces a cost-effective, high-performance approach to achieving wafer level vacuum packaging (WLVP) for MEMS-based uncooled infrared sensors. Reliable and hermetic packages for MEMS devices are achieved using a cap wafer that is formed using two silicon wafers, where one wafer has precise grating/moth-eye structures on both sides of a double-sided polished wafer for improved transmission of over 80% in the long-wave infrared (LWIR) wavelength region without the need for an AR coating, while the other wafer is used to form a cavity. The two wafers are bonded using Au-In transient liquid phase (TLP) bonding at low temperature to form the cap wafer, which is then bondelectrical and Electronics d to the sensor wafer using glass frit bonding at high temperature to activate the getter inside the cavity region. The bond quality is assessed using three methods, including He-leak tests, cap deflection, and Pirani vacuum gauges. Hermeticity is confirmed through He-leak tests according to MIL-STD 883, yielding values as low as 0.1 × 10-9 atm·cc/s. The average shear strength is measured as 23.38 MPa. The package pressure varies from 133-533 Pa without the getter usage to as low as 0.13 Pa with the getter usage.

Wafer and chip-level characterization of edge-coupled photonic integrated circuits by cascaded grating couplers and spot-size converters

This study presents an efficient testing process for characterizing silicon photonic ICs. This process utilizes a coupling structure that integrates grating couplers and spot-size converters for efficient testing both at the chip and wafer levels, respectively. By leveraging wafer-level testing to estimate the characteristics of final chip-level devices, we anticipate a reduction in testing costs. To demonstrate the validity of the proposed testing process, we fabricated and measured silicon-on-insulator ring resonator devices on both wafer and chip levels. The results showed good agreement between the two levels of measurement, validating the effectiveness of our proposed testing process.

Minimizing Recess of Cu Pad on Hybrid Bonding with SiCN via Non-selective Chemical Mechanical Polishing and Post-cleaning Steps

Hybrid bonding has become a promising approach to realizing fine pitch interconnection via bonding for both the wafer level and die level. The morphology and cleanliness of the bonding surface are critical to ensure a high yield. Therefore, surface planarization by chemical mechanical polishing (CMP) is considered a key process. The recess on the Cu pad must be controlled to be less than 5 nm by adjusting the removal rate between the Cu, the barrier layer, and the bonding dielectric layer. Conventionally, SiO2 has served as the bonding dielectric. However, SiCN is considered a promising dielectric because of its high bonding strength, suppression of voids, and ability to function as a Cu diffusion barrier. Here, we investigated simultaneous Cu, barrier, and SiCN CMP for hybrid bonding. Post-CMP processes such as cleaning and activation were also assessed. The results revealed that the removal rate of the three materials could be adjusted by dilution of the slurry and oxidizer. Lower selectivity was achieved at a certain dilution rate in an alkaline barrier slurry. Plasma activation revealed that the Cu passivation layer formed during cleaning was removed. Therefore, residues from CMP and post-CMP processes did not affect Cu prior to the hybrid bonding.

Quantum Graphene Asymmetric Devices for Harvesting Electromagnetic Energy.

We present here the fabrication at the wafer level and the electrical performance of two types of graphene diodes: ballistic trapezoidal-shaped graphene diodes and lateral tunneling graphene diodes. In the case of the ballistic trapezoidal-shaped graphene diode, we observe a large DC current of 200 µA at a DC bias voltage of ±2 V and a large voltage responsivity of 2000 v/w, while in the case of the lateral tunneling graphene diodes, we obtain a DC current of 1.5 mA at a DC bias voltage of ±2 V, with a voltage responsivity of 3000 v/w. An extended analysis of the defects produced during the fabrication process and their influences on the graphene diode performance is also presented.

A Study on h‐BN Resistive Switching Temporal Response

AbstractPrevious work that studied hexagonal boron nitride (h‐BN) memristor DC resistive‐switching characteristics is extended to include an experimental understanding of their dynamic behavior upon programming or synaptic weight update. The focus is on the temporal resistive switching response to driving stimulus (programming voltage pulses) effecting conductance updates during training in neural network crossbar implementations. Test arrays are fabricated at the wafer level, enabled by the transfer of CVD‐grown few‐layer (8 layer) or multi‐layer (18 layer) h‐BN films. A comprehensive study of their temporal response under various conditions–voltage pulse amplitude, edge rate (pulse rise/fall times), and temperature–provides new insights into the resistive switching process toward optimized devices and improvements in their implementation of artificial neural networks. The h‐BN memristors can achieve multi‐state operation through ultrafast pulsed switching (< 25 ns) with high energy efficiency (≈10 pJ pulse−1).

Nanosecond laser induced periodic silicon microstructures for broadband antireflective applications

Laser-driven micro/nano-texturing is a remarkably efficient and cost-effective technique, having diverse applicability in the realm of photonics, optoelectronics, and photovoltaics. Here, we demonstrate the high-intensity nanosecond laser-matter interactions for periodic micro/nanostructures on silicon, exclusively to emphasize the effects of laser parameters for large-scale integration. A wide range of periodic structure rapid fabrication over a wafer level is systematically studied for optimised parameters using nanosecond laser pulses (1064 nm, 50 ns) at different pulse repetition rates ranging from 10 to 40 kHz. A comprehensive understanding based on physical, structural, and optical studies reveals a strong correlation between the formation of nano/microstructure morphology and the laser parameters. The laser-matter interactions result in trench-like periodic patterns, formation of nanostructure agglomerations as light-trap-centres on the silicon surface. Such nano/micro periodic structures provide a dominant reduction in reflection losses of up to 80 % over a broad UV-NIR spectral region. The studies further demonstrate that the periodic structural patterns could also be potentially utilised for large-scale optical diffraction applications. In addition, the extra layer coating of Silicon Nitride (Si3N4) on the textured silicon further reduces the reflection losses, which is an added advantage of integrated silicon technology. The present work could open a commercial pathway for the rapid fabrication of nanosecond laser-based nanotexturing and periodic grating structures, enabling significantly reduced reflection and improved light trapping in large-scale Silicon-based applications due to its speed, repeatability, and high precision.

Process Development of Aluminum Electroplating from an Ionic Liquid on 150 mm Wafer Level.

This paper focuses on the development of electroplating on 150 mm wafer level for microsystem technology applications from 1-Ethyl-3-methylimidazolium chloride (EMImCl) with Aluminumtrichloride (AlCl3). The deposition was carried out on 150 mm wafers with Au or Al seed layers deposited by physical vapor deposition (PVD). The electrodeposition was carried out using pattern plating. On the Au seed layer, bipolar pulse plating was applied. Compared to the Au seed layer, the electrodeposition on the Al seed layer was favorable, with lower current densities and pulsing frequencies. Utilizing the recurrent galvanic pulses and avoiding ionic liquid convection, inhomogeneities lower than 15% were achieved with a laboratory plating cell. One major aspect of this study was the removal of the native Al oxide prior to deposition. It was investigated on the chip and wafer levels using either current- or potential-controlled removal pulses. This process step was affected by the plasma treatment of the wafer, thus the surface free energy, prior to plating. It turned out that a higher surface free energy hindered proper oxide removal at a potential of 3 V. The theory of oxide breakdown based on electrostriction force via the electrical field was applied to discuss the findings and to derive conclusions for future plating experiments.

52‐2: Invited Paper: 1µm Nanowire Based MicroLED Chips for Efficient and High Performance Smart Watch Displays

One of the microLED direct view display major challenges is to find ways of drastically dropping the cost, for instance by reducing the microLED size, simplifying the assembly process, and improving the assembly yield.Aledia has developed a 3D nanowire (NW) microLED technology on 8” silicon wafers which has the outstanding capability to keep the same efficiency for <4µm size devices containing only 1NW as for larger devices containing hundreds of NWs. This technology provides similar efficiency as well as electro‐optical parameters (I‐V and Emission Spectra) whatever the microLED size. Over 30% Wall Plug Efficiency (WPE) is obtained and 3% WPE standard deviation is measured at wafer level as well as a wavelength standard deviation as low as 1.5 nm. Those results show that our technology allowsthe manufacturing of micron size microLEDs on a Si platform without experiencing a loss of efficiency with size reduction. We will present our technology and its performance. Based on our microLED we will also propose a cost competitive and energy efficient direct‐view smartwatch display architecture.

On the quality of commercial chemical vapour deposited hexagonal boron nitride

The semiconductors industry has put its eyes on two-dimensional (2D) materials produced by chemical vapour deposition (CVD) because they can be grown at the wafer level with small thickness fluctuations, which is necessary to build electronic devices and circuits. However, CVD-grown 2D materials can contain significant amounts of lattice distortions, which degrades the performance at the device level and increases device-to-device variability. Here we statistically analyse the quality of commercially available CVD-grown hexagonal boron nitride (h-BN) from the most popular suppliers. h-BN is of strategic importance because it is one of the few insulating 2D materials, and can be used as anti-scattering substrate and gate dielectric. We find that the leakage current and electrical homogeneity of all commercially available CVD h-BN samples are significantly worse than those of mechanically exfoliated h-BN of similar thickness. Moreover, in most cases the properties of the CVD h-BN samples analysed don’t match the technical specifications given by the suppliers, and the sample-to-sample variability is unsuitable for the reproducible fabrication of capacitors, transistors or memristors in different batches. In the short term, suppliers should try to provide accurate sample specifications matching the properties of the commercialized materials, and researchers should keep such inaccuracies in mind; and in the middle term suppliers should try to reduce the density of defects to enable the fabrication of high-performance devices with high reliability and reproducibility.

Silicon Nanoantennas for Ultra‐Compact, High‐Speed and Low‐Power Consumption Electro‐Optic Modulators

AbstractTo keep pace with the expanding data capacity in modern communications and increasing on‐chip integration density, it is highly desirable to have electro‐optic modulators featured with compact footprint, large modulation bandwidth, low energy consumption, and full complementary metal‐oxide‐semiconductor (CMOS) compatibility. Here, this work experimentally demonstrates a high‐speed electro‐optic modulator in the telecommunication wavelength range made of a 1D chain resonator of Mie‐resonant silicon nanoparticles. The modulator exploits the plasma dispersion effect and works in the carrier depletion configuration. The resulting large modulation bandwidth over 40 GHz and low energy consumption of 23 fJ bit−1 are attributed to its ultra‐compact footprint of 10 µm2. The open eye diagrams are measured up to 40 Gbits s−1. The modulators are fabricated at wafer level by a silicon photonic foundry using CMOS‐compatible process. This modulator shows promise for achieving higher integration density and larger modulation bandwidth. It can be added to the existing on‐chip device building blocks library and used for a wide range of applications, including data communication, quantum photonics, and non‐reciprocal optics.